The object of this research is to develop a solution for band-limited channels. Backplane channels and GPON channels are investigated to apply an equalization technique. Different lengths of backplane channels are measured with different signal speeds to investigate the channel performance. Also a GPON system with different fiber lengths is designed and set up in a lab to measure the BER performance. The GPON system utilizes a Fabry-Perot laser for the most economical solution. After the circuits are fabricated, they are inserted into the system to measure the performance of the channels with equalizers. Both the backplane and the GPON system show successful channel improvement in measured eye diagrams and BER. To expedite the procedure and eventually build an adaptive system which could be inserted and self-optimizing, we found it essential to monitor the output of the equalizer. A novel analog way to achieve this goal is suggested. All the equalizers mentioned in this dissertation have one summing node to add up all the values from VGAs. This structure is very efficient, but in the event that there are too many VGAs, it draws too much current through the one node. This issue is dealt with by the design of two nine tap equalizers, which are compared to assess the difference in performance between the unbalanced structure and the balanced structure.

Cette thèse propose des nouvelles méthodes de conception et de test des systèmes CMOS intégrés, permettant d'augmenter la fiabilité et la tolérance aux pannes en technologies submicroniques profonds, et répondre à l'augmentation des défauts non-décelables au test de fabrication et à la sensibilité accrue aux aléas dus aux rayons cosmiques. Pour améliorer la détection de fautes dans les circuits CMOS complexes, des capteurs de courant intégrés à haute vitesse et sensibilité fonctionnant sous faible tension d'alimentation sont proposés. Les algorithmes de mesure de courants IDDQ, développés parallèlement, sont analysés et optimisés en synergie avec des techniques de conception à faible consommation. L'utilisation de capteurs de courant a été étendue à un test en-ligne qui permet de détecter les fautes permanentes dans les applications critiques, et de corriger les erreurs dans les mémoires SRAM par codage de parité. Cette approche a été validée par des tests sous rayonnement sur des circuits prototypes. Une stratégie de conception de circuits CMOS immunes aux aléas indépendante de la technologie utilisée a été ensuite développée, basée sur des techniques de redondance locale. Sa validation expérimentale par des tests sous rayonnement a été effectuée sur des circuits prototypes réalisés en technologies CMOS commerciales de 1,2 , 0,8 et 0,25 microns. L'analyse des techniques de durcissement implantées a été faite à l'aide de méthodes de test intégré et en utilisant des équipements laser aux impulsions. Des mécanismes d'erreurs et une sensibilité aux aléas liés à la topologie ont été mis en évidence et caractérisés. En réponse, on a élaboré des règles de conception spécifiques, conduisant à un durcissement topologique aux aléas. Une bibliothèque de cellules séquentielles durcies a été développée, en vue de son utilisation dans un modem ASIC dédié à un satellite expérimental qui sera mis en orbite en 2001.

Zugl.: Berlin, Techn. Univ., Diss., 2009

Affinity-based biosensors, or in short biosensors, are extremely powerful and versatile analytical tools which are used for the detection of a wide variety of bio-molecules. In recent times, there has been a need for developing low-cost and portable affinity-based biosensor platforms. Such systems need to have a high density of detection sites (i.e biosensing elements) in order to simultaneously detect multiple analytes in a single sample. This has led to the creation of integrated biosensors, which make use of integrated circuits (ICs) for bio-molecular detection. In such systems, it has been demonstrated that by taking advantage of the capabilities of semiconductor and very large scale integrated (VLSI) circuit fabrication processes, it is possible to build compact miniaturized biosensors, which can be used in wide variety of applications such as in molecular diagnostics and for environmental monitoring. Among the various detection modalities for biosensors, Electrochemical Impedance Spectroscopy (EIS) permits real-time detection and has label-free detection capabilities. EIS is fully electronic in nature. Hence, it can be implemented using standard IC technologies. The versatility and ease of integration of EIS makes it a promising candidate for developing integrated biosensor platforms. In this thesis, we first examine the underlying principles of EIS method of biosensing. By analyzing an immunosensor assay as an example, we show that EIS based biosensing is a highly sensitive detection method, which can be used for the detection of a wide variety of analytes. Since EIS relies on small impedance changes in order to perform detection, it requires highly accurate models for the electrode-electrolyte systems. Hence, we also introduce a compact modeling technique for the distributed electrode-electrolyte systems with non-uniform electric fields, which is capable of modelling noise and other non-idealities in EIS. In the second part of this thesis, we describe the design and implementation of an integrated EIS biosensor array, built using a standard complementary metal-oxide-semiconductor (CMOS) process. The chip is capable of measuring admittance values as small as 10nS and has a wide dynamic range (90dB) over a wide range of frequencies (10Hz-50MHz). We also report the results obtained from the DNA and protein detection experiments performed using this chip. / text

Today, there is an ever-growing demand for compact, and energy autonomous, implantable biomedical sensors. These devices, which continuously collect in vivo physiological data, are imperative in the next generation patient monitoring systems. One of the fundamental challenges in their implementation, besides the obvious size constraints and the tissue-to-electronics biocompatibility impediments, is the efficient means to wirelessly deliver power to them. This work addresses this challenge by demonstrating an energy-autonomous and fully-integrated implantable sensor chip which takes advantage of the existing on-chip photodiodes of a standard CMOS process as photovoltaic (PV) energy-harvesting cells. This 2.5 mm × 2.5 mm chip is capable of harvesting [mu]W’s of power from the ambient light passing through the tissue and performing real-time sensing. This system is also MRI compatible as it includes no magnetic material and requires no RF coil or antennae. In this dissertation, the optical properties of tissue and the capabilities of the CMOS integrated PV cells are studied first. Next, the implementation of an implantable sensor using such PV devices is discussed. The sensor characterizing and the in vitro measurement results using this system, demonstrate the feasibility of monolithically integrated CMOS PV-driven implantable sensors. In addition, they offer an alternative method to create low-cost and mass-deployable energy autonomous ICs in biomedical applications and beyond. / text

In the past decade, there has been great motivation to improve the efficiency of power amplifiers (PAs) in handset transmitter systems in order to address critical issues such as poor battery life and excessive heat. Currently, the focus lies on high data rate applications such as wideband code division multiple access (WCDMA) and long term evolution (LTE) standards due to the stringent efficiency and linearity requirements on the PA. This thesis describes a simulation-based study of techniques for enhancing the efficiency of a CMOS power amplifier for WCDMA and LTE applications. The primary goal is to study the concepts of envelope and average power tracking in simulation and to demonstrate the effectiveness of these supply modulation techniques on a CMOS PA design. The P1dB and IMD performance of a Class A/AB CMOS PA has been optimized to operate with high peak-to-average modulation with WCDMA and LTE signals. Behavioral models of envelope and average power tracking are implemented using proposed algorithms, and a system-level analysis is performed. Envelope tracking is seen to offer a peak PAE improvement of 15% for WCDMA, versus a fixed voltage supply, while average power tracking renders a maximum efficiency gain of 9.8%. Better than -33dBc adjacent channel leakage-power ratio (ACLR) at 5MHz offset and EVM below 4% are observed for both supply tracking techniques. For LTE, envelope and average power tracking contribute to a peak PAE enhancement of 15.3% and 7%, respectively. LTE ACLR begins failing the -30dBc specification above 22.5dBm output power during envelope tracking operation in the PA implementation described here. / text

Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions. / text

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(情報学) / 甲第19137号 / 情博第583号 / 新制||情||102 / 32088 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 髙木 直史, 教授 佐藤 高史 / 学位規則第4条第1項該当

This work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices. / text

Total ionizing dose (TID) radiation effects modeling and simulation on digital, analog and mixed signal systems remains a significant bottle neck in the development of radiation-hardened electronics. Unverified modeling techniques and the very high computational cost with today's commercial simulation tools are among the primary hindrances to the timely hardened IC design, particularly to the design in commercially available processes. SPICE-based methods have been used for total dose radiation degradation simulations. While SPICE is effective in predicting the circuit behavior under circumstances when the electrical parameters stay constant during operation, it's not effective predicting aging behavior with gradual change with time. Behavioral modeling language, such as VHDL-AMS is needed to effectively capture the time-dependent degradation in these parameters in response to environmental stresses, such as TID radiation.This dissertation describes a method for accurate and rapid TID effect simulation of complex mixed-signal circuits. The method uses a hierarchical structure where small sub-circuits, such as voltage comparators, references, etc. are simulated using SPICE. These SPICE simulations of small circuits for multiple radiation doses are used to tune behavioral VHDL-AMS models for the sub-circuits. The created behavioral models therefore contain the electrical circuit behavior combined with the radiation response. The entire combined system is then simulated using VHDL-AMS.In a simulation experiment that was used to validate the speed and accuracy of the new method, a commercial 8-bit sub-ranging analog to digital converter netlist containing more than 2000 MOS transistors was simulated with TID models using a contemporary SPICE-based method and the new method. The new method shortened the simulation time by three orders of magnitude, while accuracy remained within reasonable limits compared to the SPICE-based method. Moreover, the automated procedures for circuit node bias monitoring, TID model replacement and result collection that are included in the simulation code of the new method decreased the "hands-on" engineering work significantly. Results from an experiment where the new TID effect simulation method was used as a hardness assurance test procedure for integrated circuits designed to be operated in radiation-harsh environments are also included in this dissertation.