The dominant powder scintillator in most medical imaging modalities for decades is Gd2O2S:Tb due to the very good intrinsic properties and overall efficiency. Except for Gd2O2S:Tb there are alternative powder phosphor scintillators like Lu2SiO5:Ce and Gd2O2S:Eu that has been suggested for use in various medical imaging modalities. Gd2O2S:Eu emits red light and can be combined mainly with digital imaging devices like CCDs and CMOS based detectors. The purposes of the present thesis, is to investigate the fundamental imaging performance of a high resolution CMOS based imaging sensor combined with custom made Europium (Eu3+) activated Gd2O2S screens in terms of Modulation Transfer Function (MTF), Normalized Noise Power Spectrum (NNPS), Detective Quantum Efficiency (DQE), Noise Equivalent Quanta (NEQ) and Information Capacity (IC) covering the mammography and general radiography energy ranges. The CMOS sensor was coupled to two Gd2O2S:Eu scintillator screens with coating thicknesses of 33.3 and 65.1 mg/cm2, respectively, which were placed in direct contact with the photodiode array. The CMOS photodiode array, featuring 1200x1600 pixels with a pixel pitch of 22.5 m , was used as an optical photon detector. In addition to frequency dependent parameters (MTF, NPS, DQE) characterizing image quality, image information content was assessed through the application of information capacity (IC). The MTF was measured using the slanted-edge method to avoid aliasing while the Normalized NPS (NNPS) was determined by two-dimensional (2D) Fourier transforming of uniformly exposed images. Both parameters were assessed by irradiation under the RQA-5 protocol (70kVp digital-radiography) recommended by the International Electrotechnical Commission Reports 62220-1 and the W/Rh, W/Ag beam qualities (28kVp digital-mammography). The DQE was assessed from the measured MTF, NNPS and the direct entrance surface air-Kerma (ESAK) obtained from X-ray spectra measurement with a portable cadmium telluride (CdTe) detector. The spectral matching factor between the optical spectra emitted by the Gd2O2S:Eu and the Gd2O2S:Tb screens and the CMOS optical sensor, evaluated in the present study, was 1 and 0.95 respectively. The ESAK values ranged between 11.2-87.5 Gy , for RQA-5, and between 65.8-334 Gy , for W/Rh, W/Ag beam qualities. It was found that the detector response function was linear for the exposure ranges under investigation. Under radiographic conditions the MTF of the present system was found higher than previously published MTF data for a 48 m CMOS sensor, in the low up to medium frequency ranges. DQE was found comparable, while the NNPS appeared to be higher in the frequency range under investigation (0–10 cycles/mm). NEQ reached a maximum (73563 mm-2) in the low frequency range (1.8 cycles/mm), under the RQA 5 (ESAK: 11.2 Gy ) conditions. IC values were found to range between 1730-1851 bits/mm2. Under mammographic conditions MTF, NNPS and NEQ were found comparable to data previously published for the 48 m CMOS sensor while the DQE was found lower. The corresponding IC values were found ranging between 2475 and 2821 bits/mm2. The imaging performance of europium (Eu3+) activated Gd2O2S screens in combination to the CMOS sensor, investigated in the present study, was found comparable to those of Terbium (Tb) activated Gd2O2S screens (combined with the CMOS sensor). It can be thus claimed that red emitting phosphors could be suitably used in digital imaging systems, where the Silicon (Si) based photodetectors are more sensitive to longer wavelength ranges, and particularly in the red wavelength range. / -

Electronic dispersion compensation (EDC) of intermodal dispersion on short multimode fiber (MMF) links operating at 40 Gb/s is investigated through system level simulations and the design of two analog integrated circuit (IC) equalizers. System simulations using worst-case MMF link models show the effectiveness of a 2-tap baud spaced finite impulse response (FIR) equalizer for 40-m links, and a second-order Tbaud/2 infinite impulse response (IIR) equalizer for 50-m links. An IIR filter topology suitable for IC implementation with double loops and multiple delay sections was developed. The 2-tap FIR and the IIR equalizer are implemented in UMC 0.13-um and STM 90-nm CMOS processes respectively. Measurements demonstrate the FIR and IIR equalizing 38-Gb/s and 30-Gb/s cable channels respectively. To the author's knowledge, the double-loop multi-delay IIR equalizer is the first integrated traveling-wave equalizer utilizing poles as a means of frequency boosting, contrasting the conventional FIR technique of utilizing zeros.

Electronic dispersion compensation (EDC) of intermodal dispersion on short multimode fiber (MMF) links operating at 40 Gb/s is investigated through system level simulations and the design of two analog integrated circuit (IC) equalizers. System simulations using worst-case MMF link models show the effectiveness of a 2-tap baud spaced finite impulse response (FIR) equalizer for 40-m links, and a second-order Tbaud/2 infinite impulse response (IIR) equalizer for 50-m links. An IIR filter topology suitable for IC implementation with double loops and multiple delay sections was developed. The 2-tap FIR and the IIR equalizer are implemented in UMC 0.13-um and STM 90-nm CMOS processes respectively. Measurements demonstrate the FIR and IIR equalizing 38-Gb/s and 30-Gb/s cable channels respectively. To the author's knowledge, the double-loop multi-delay IIR equalizer is the first integrated traveling-wave equalizer utilizing poles as a means of frequency boosting, contrasting the conventional FIR technique of utilizing zeros.

This thesis presents the design of radio-frequency (RF) tunable active inductors (TAIs) with independent inductance (L) and quality factor (Q) tuning capability, and their application in the design of RF tunable phase shifters and directional couplers for wireless transceivers. The independent L and Q tuning is achieved using a modided gyrator-C architecture with an additional feedback element. A general framework is developed for this Q- enhancement technique making it applicable to any gyrator-C based TAI. The design of a 1.5V, grounded, 0.13um CMOS TAI is presented. The proposed circuit achieves a 0.8nH-11.7nH tuning range at 2GHz, with a peak-Q in excess of 100. Furthermore, printed and integrated versions of tunable positive/negative refractive index (PRI /NRI) phase shifters, are presented in this thesis. The printed phase shifters are comprised of a microstrip transmission-line (TL) loaded with varactors and TAIs, which, when tuned together, extends the phase tuning range and produces a low return loss. In contrast, the integrated phase shifters utilize lumped L-C sections in place of the TLs, which allows for a single MMIC implementation. Detailed experimental results are presented in the thesis. As an example, the printed design achieves a phase of -40 to +34 degrees at 2.5GHz. As another application for the TAI, a reconfigurable CMOS directional coupler is presented in this thesis. The proposed coupler allows electronic control over the coupling coefficient, and the operating frequency while insuring a low return loss and high isolation. Moreover, it allows switching between forward and backward operation. These features, combined together, would allow using the coupler as a duplexer to connect a transmitter and a receiver to a single antenna. Finally, a planar electronically steerable patch array is presented. The 4-element array uses the tunable PRI/NRI phase shifters to center its radiation about the broadside direction. This also minimizes the main beam squinting across the operating bandwidth. The feed network of the array uses impedance transformers, which allow identical interstage phase shifters. The proposed antenna array is capable of continuously steering its main beam from -27 to +22 degrees of the broadside direction with a gain of 8.4dBi at 2.4GHz.

This thesis examines the use of two coupled loops as an alternative method of connection for high frequency signals between passive elements on microwave laminates and integrated circuits; replacing traditional interconnect methods such as wire bonds and solder bumps which require costly back end of line processing. The loops harness both electric and magnetic fields in order to create the interconnection, and can be placed around the perimeter of the IC; here they do not interfere with placement of the existing electronics on the chip, or occupy space which may be required for large components such as spiral inductors. A parametric model for these coupled loops was developed in this thesis. This model allows for rapid initial dimension choice when provided a variety of different parameters such as the IC process geometry, and loop stack geometry. Once initial dimensions are obtained from the model, full-wave simulation can be used to finalize the design and examine effects of process design rules such as metal density requirements. Following model development a prototype system, consisting of a two metallic loops (one located on a low-loss microwave laminate, the other on a 0.13 u m CMOS IC), was fabricated. These loops were then stacked in order to couple the signal from a planar antenna array (printed on the laminate) onto the IC. This antenna-to-chip system was simulated and measured to have center frequencies of 25 GHz and 23 GHz respectively, with a peak gain greater than 5 dBi at the beams broadside (8 dBi in simulation). These results agree quite well, with discrepancies arising primarily from the presence of adhesive between the loops. This adhesive wicked underneath the IC during assembly, which was not accounted for during simulation, but can easily be done so. The radiation pattern from the antenna was measured to have a HPBW of 16 degrees in the elevation plane and 100 degrees in the azimuth plane. These correspond nicely with simulated results and produce a suitable system for automotive radar application; where harsh environments present difficulties to current interconnects such as wire bonds. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-09-09 21:55:06.971

Dans la réalisation de circuits intégrés hybrides électroniques - photoniques pour les réseaux télécom, les modulateurs intégrés plasmoniques pourront jouer un role essentiel de codage de l'information en signaux optiques. Cette thése montre la réalisation d'une approche modulateur plasmonique a effet de champ, intégrée en silicium en utilisant les technologies CMOS standards. Ce modulateur MOS plasmonique présente diverses propriétés intéressantes, a savoir un confinement optique fort, permettant une augmentation de l'interaction lumiére matiére. Ces modulateurs plasmoniques permettent aussi de réduire l'inadéquation entre la taille des dispositifs en photonique Si et celle de l' électronique, ce qui permet d'envisager une convergence de leur fabrication en technologie VLSI sur une meme puce. Le modulateur étudié dans ce mémoire repose sur l'accumulation de porteurs dans un condensateur MOS a grille cuivre integer dans un guide d'onde en silicium, nécessitant aux technologies front end et back end Cu d etre combinés de quelques nanométres l'une de l'autre. Nous présentons aussi de nouveaux designs pour injecter de la lumiére a partir de guide d'onde SOI dans un guide a nanostructure plasmonique et les mesures d'une modulation électro-optique dans les structures MOS plasmoniques

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.

High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. Although Hf-based technology has become the de facto industry standard for high-k/metal gate MOSFETs, problematic long-term scalability has motivated the research of novel materials and solutions to fulfill the target performances expected of gate stacks in future technology nodes. In this work, integration of a high-k interfacial layer has been identified as the most promising approach to improve gate dielectric scalability, since this technology presents the advantage of potential compatibility with both current Hf-based and plausible future higher-k materials. Thulium silicate has been selected as candidate material for integration as interfacial layer, thanks to its unique properties which enabled the development of a straightforward integration process achieving well-controlled and repeatable growth in the sub-nm thickness regime, a contribution of 0.25+-0.15 nm to the total EOT, and high quality of the interface with Si. Compatibility with industry-standard CMOS integration flows has been kept as a top priority in the development of the new technology. To this aim, a novel ALD process has been developed and characterized, and a manufacturable process flow for integration of thulium silicate in a generic gate stack has been designed. The thulium silicate interfacial layer technology has been verified to be compatible with standard integration flows, and fabrication of high-k/metal gate MOSFETs with excellent electrical characteristics has been demonstrated. The possibility to achieve high performance devices by integration of thulium silicate in current Hf-based technology has been specifically demonstrated, and the TmSiO/HfO2 dielectric stack has been shown to be compatible with the industrial requirements of operation in the sub-nm EOT range (down to 0.6 nm), reliable device operation over a 10 year expected lifetime, and compatibility with common threshold voltage control techniques. The thulium silicate interfacial layer technology has been especially demonstrated to be superior to conventional chemical oxidation in terms of channel mobility at sub-nm EOT, since the TmSiO/HfO2 dielectric stack achieved ~20% higher electron and hole mobility compared to state-of-the-art SiOx/HfO2 devices at the same EOT. Such performance enhancement can provide a strong advantage in the EOT-mobility trade-off which is commonly observed in scaled gate stacks, and has been linked by temperature and stress analyses to the higher physical thickness of the high-k interfacial layer, which results in attenuated remote phonon scattering compared to a SiOx interfacial layer achieving the same EOT. / <p>QC 20140512</p>

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator's frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA.

Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded. This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed. / Report code: LiU-TEK-LIC-2006:22