<p dir="ltr">Technological advancements in the semiconductor industry have led to the development of fast, low-power, and high-performance electronic devices. With evolving process technologies, the size of an electronic device has greatly reduced, and the number of features a single device can support has steadily increased. To achieve this, billions of transistors are integrated into small electronic chips leading to an increase in the complexity of manufacturing processes. Electronic chips that are manufactured using such complex manufacturing processes are prone to have a large number of defects that are difficult to test, and cause reliability issues. To tackle these issues and produce highly reliable chips, there is a growing need to test each manufactured chip thoroughly. This requires the application of a large number of tests by a tester. The cost of testing an electronic chip primarily depends on the storage requirements of the tester, and the test application time required. The large number of tests required to rigorously test each chip leads to an increase in the testing cost. Earlier works reduced the testing cost by reducing the input storage requirements of the tester. The input storage requirements are reduced by using each stored test on the tester to apply several different tests to the circuit. Several different tests are also applied based on each stored test to improve the quality of a test set. The goal of this thesis is to aide in producing reliable chips, by creating test sets that can detect faults from different fault models. The test sets are created by improving the quality of a test set. </p><p><br></p><p dir="ltr">First, test sets with low storage requirements are produced for defect detection. A base test set is generated and stored. Each stored test is perturbed to produce several different tests. Algorithms are then described in two different scenarios to select a subset of the perturbed tests. The selected subset of tests improves the quality of defect detection with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Next, test sets with low-storage requirements are produced for defect diagnosis. A fault detection test set is generated and stored. Each stored test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests to be used as diagnostic tests. The diagnostic test set selected improves the quality of defect diagnosis with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Finally, storage-aware test sets are produced targeting several fault models in two steps. In the first step, tests in a base test set are replaced with improved tests to produce an improved test set. The improved test set is stored, and it improves the quality of defect detection with no increase in the storage requirements. In the second step, each improved test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests. The selected subset of tests further improves the quality of defect detection with a minimal increase in the input storage requirements.</p>

<p dir="ltr">Semiconductor technology has propelled human society into the information age, and that progress continues. Silicon CMOS device has been aggressively scaled down to 5 nm technology node. To further boost the on-state performance, MOS technology based on high-mobility channels such as III-V and Ge have been intensively studied. 3D structures such as FinFETs and gate-all-around (GAA) FETs are also applied to III-V and Ge to improve the electrostatic control of the channels for the ultimate scaling. </p><p><br></p><p dir="ltr">Traditional semiconductor device characterization techniques are inapplicable to devices created through these novel materials and device structures. This work applies various techniques to characterize a wide variety of semiconductor devices, in addition to presenting novel techniques studying the reliability of commercial off the shelf (COTS) products. Finally, the design of an ultra-low-power RF ASIC implementing wireless neural recording and stimulation, designed for cranial implantation, will be presented.</p>

Les circuits asynchrones se démarquent des circuits synchrones par une modularité quasi-parfaite, l'absence d'horloge, et le contrôle local. Ils tendent à constituer une sérieuse alternative pour pallier aux problèmes posés par l'intégration en silicium d'applications de plus en plus complexes. Le goulot d'étranglement principal pour l'adoption de la conception des circuits asynchrones se situe au niveau du manque de méthodologies et d'outils puissants pour ce type de conception. Ce travail de thèse porte sur la définition d'une méthodologie de conception de circuits intégrés asynchrones micropipeline. La synthèse micropipeline est une approche qui exploite à la fois les outils commerciaux de synthèse pour le chemin de données, et la synthèse de contrôleurs asynchrones pour le contrôle. La méthodologie générale pour la modélisation et la synthèse de circuits asynchrones est basée sur la spécification dite DTL (Data Transfer Level) qui définit une façon d'écrire les codes sources garantissant une synthèse rapide et systématique pouvant cibler plusieurs styles de circuits asynchrones. Cette méthode de conception part d'une spécification basée sur un langage de haut niveau (CHP ou Concurrent Hardware Processes). Elle permet en sortie de générer des circuits en portes logiques élémentaires et en portes de Muller. Il a été procédé à un prototypage de cette méthode de synthèse. Ce prototype est conçu pour être intégré dans l'outil de conception automatique de circuits asynchrones TAST (Tima Asynchronous Synthesis Tool) dont le synthétiseur génère des circuits asynchrones QDI, pour l'étendre à la génération de circuits micropipelines.

Les circuits asynchrones se caractérisent par l'absence d'horloge. Ils offrent des propriétés intéressantes pour l'intégration de systèmes dans les technologies submicroniques telles que robustesse, faible bruit, faible consommation, bonne modularité. Cependant, le manque de méthodes et outils de conception est un frein à leur développement. Les travaux présentés dans cette thèse portent sur la définition d'une méthodologie de conception de circuits intégrés asynchrones quasi-insensibles aux délais. Celle-ci permet d'une part la modélisation dans un langage de haut-niveau et la simulation dans un environnement standard et d'autre part la génération de circuits uniquement constitués de cellules standard. Cette méthodologie a été appliquée à l'étude et à la réalisation d'un processeur RISC 16-bit. Son architecture originale permet d'effectuer l'envoi des instructions dans l'ordre et de les terminer dans le désordre. Ce prototype fabriqué dans la technologie 0.25um de STMicroelectronics est l'un des processeurs asynchrones le plus rapide réalisé à ce jour

Low-power digital design has been a widely researched area for the past twenty years. The growing demand for mobile computing made low power an especially important quality for such systems and encouraged researchers to find new ways of reducing power dissipation. Aggressive voltage scaling was recently published as a new paradigm for reducing power dissipation in digital circuits and the use of soft-edge flip-flops is one such technique in this category. In this thesis, we propose a soft-edge flip-flop topology that is better suited to implement the soft-edge property compared to the previously published implementations. In addition, we present the effectiveness of the soft-edge flip-flop technique by applying it to a practical VLSI design implemented with the TSMC 0.18um standard cell library. Using HSIM transistor-level SPICE simulator, we show that at least 25% power reduction is achievable in the whole circuit with a negligible area overhead. / text

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<div>With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed.</div><div><br></div><div>The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages.</div><div><br></div><div>The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of 425mV.</div><div><br></div><div>FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.</div>

<p>        The last decade has witnessed an explosive growth in highly data-centric applications such as Internet of Things (IoT) and Artificial Intelligence (AI). Such applications demand highly efficient data storage and processing, especially when the systems operate under high energy/resource constraints, such as in intermittent-powered systems or edge AI platforms. Therefore, at the hardware level, high storage capacity along with low power operations has become more crucial than ever. Although conventional silicon-based complementary metal-oxide semiconductor (CMOS) has brought great prosperity to the semiconductor industry to date, enabling high-performance computing, increasing leakage energy and low cell density hinder their ability to sustain their benefits at scaled nodes and meet the demands of emerging data-intensive workloads. On the other hand, emerging non-volatile memories (NVMs) have gained much attention due to their distinct advantages over CMOS, such as zero leakage, high density, and non-volatility. However, they suffer from issues associated with high write power, endurance and/or variability. Thus, there is a need for new memory technologies that offer high density, low power and high-performance attributes to meet the data storage and efficiency demands of the new workloads. Furthermore, such technological advances need to be supported by architectural innovations. Despite hardware advances, the energy efficiency gains in traditional von-Neumann architectures are limited by power-hungry data movements between memory and processor, also known as the memory bottleneck. To alleviate this issue, in-memory computing (IMC) has emerged as a promising technique, wherein certain computations are executed within a memory macro, thus reducing processor-memory transactions. Along similar lines, incorporating non-volatile storage in logic state elements, such as flip-flops, has gained much attention for intermittently-powered systems, wherein the state of the processor is efficiently backed-up in the local non-volatile memory in the event of a power failure. Such techniques enabling logic-memory synergy reduce compute, storage, and/or communication costs and thus can be highly promising for future computing platforms. However, existing techniques for logic-memory fusion suffer from key design bottlenecks that need to be mitigated via extensive technology-circuit-architecture co-design. In this dissertation, we address some of the issues associated with data storage and processing by exploring spin-based low-power non-volatile devices, their memory applications, and logic-memory coupling enabled by their unique technological attributes. </p> <p>      We propose spin-based devices that employ the valley-spin Hall (VSH) effect in monolayer transition metal dichalcogenides (TMDs), such as tungsten di-selenide (WSe2). With the unique features of WSe2, the proposed devices are designed to have an integrated back-gate, enabling control of the charge and spin currents in 2D TMD channel. This design leads to an access-transistor-less compact layout in memory arrays. The generated spin currents diverge into opposite directions with out-of-plane spins, allowing for the coupling of WSe2 with perpendicular magnetic anisotropy (PMA) magnets. This enables low-power write operations and facilitates differential logic encoding within a single device. Additionally, we utilize inter-layer exchange-coupling mediated by FeCo-oxide and Ta layers to electrically isolate but magnetically couple the PMA free layers. This configuration benefits read performance by achieving low series resistance in the read path. To ensure reliable inter-layer coupling and the functionality of the proposed devices, we perform micromagnetic OOMMF simulations and extensively investigate the impact of process variations on the exchange-coupled PMA free layers. From the simulations, we conclude that the proposed design is resilient to potential process variations arising from misalignment of the PMA free layers and reductions in exchange-coupling strength. Based on the proposed devices, we explore circuit designs for logic and memory applications. </p> <p>      First, we propose VSH effect-based non-volatile flip-flops (VSH-NVFFs) using the proposed devices to introduce non-volatility in logic targeted for intermittently powered systems. The key challenge to design such systems is to enable energy-efficient data back-up in the event of power failure. In our design, we achieve high energy-efficiency via device-circuit co-design of VSH devices and NVFFs. We propose two flavors of NVFFs: NVFF-1 with a compact design and NVFF-2 targeted for lowering data restore energy. Compared to existing giant spin Hall (GSH) effect-based NVFFs, also known as spin-orbit torque or SOT-NVFFs, our NVFFs exhibit 68%-71%, 74%-75% and 55%-59% lower normal, back-up, and restore energies, respectively. Among the proposed VSH-NVFFs, NVFF-1 exhibits 8% lower operation energy than NVFF-2, while NVFF-2 exhibits 6% lower back-up energy and 11% lower restore energy. This result suggests that NVFF-1 is more suitable for systems with a smaller number of checkpointing operations (data back-up/restore), while NVFF-2 is beneficial for systems needing a larger number of checkpointing operations. Furthermore, by conducting Monte Carlo simulations, we confirm the reliable restore operation of the proposed NVFFs.</p> <p>      Secondly, we design memory arrays using the proposed devices to gain benefits over previously proposed VSH effect-based memory designs, in which read currents flow through a highly resistive 2D TMD channel, degrading read performance. For read operations, our memory array requires a read access transistor. By sharing the read access transistor per word, we minimize the area overhead in our memory array design. The area of our bit-cell is comparable to a previously proposed VSH memory, despite the inclusion of an additional read access transistor. Additionally, with the electrical isolation of the read and write paths in our design, we achieve improvements in read performance, with reductions of 39%-42% and 36%-46% in read time and energy, respectively. However, this improvement comes at the cost of write performance, with a 1.7X and 2.0X increase in write time and energy, respectively. We also achieve a 1.1X-1.3X larger sense margin (SM) and a 1.2X-1.3X improvement in read disturb margin (RDM). Furthermore, by increasing the size of the read access transistor in our memory array, we can further improve the SM by up to 1.5X-1.6X with only a 7%-12% area increase. Our design can be particularly useful for applications that involve frequent reads and few writes, such as neural accelerators.</p> <p>      We further expand our exploration of VSH effect-based devices for implementing IMC. As XNOR-based binary neural networks (BNNs) have shown immense promise for resource-intensive AI edge systems, their implementation has been explored using SRAMs and emerging NVMs. However, these designs typically need two bit-cells (2T-2R) to encode signed weights, resulting in an area overhead. Therefore, we address this issue by proposing a compact and low-power IMC technique for XNOR-based dot products. Our approach utilizes the VSH effect in monolayer WSe2 to design XNOR bit-cells that feature an access-transistor-less compact layout and differential weight encoding in a single device (XNOR-VSH). We co-optimize the proposed VSH device and the memory arrays to enable efficient in-memory dot product computations between signed binary inputs and signed binary weights. The compactness of the proposed XNOR-VSH array leads to 4.8%-9.0% lower compute latency and 36.6%-62.5% lower compute energy, along with 49.3%-64.4% smaller area compared to spin-transfer torque magnetic RAM (STT-MRAM) and SOT-MRAM based XNOR-arrays.</p> <p>      Lastly, we explore the modeling and design of voltage-controlled spintronic devices, which have shown remarkable potential for ultra-low-power and high-speed operation empowered by magnetoelectric (ME) materials. The proposed ME device utilizes a monolayer WSe2 channel placed on top of a Cr2O3 ME dielectric, which are electrostatically controlled by top and bottom gates. To capture the electrostatics in 2D TMD and the gate-voltage-dependent ME effect, we establish a modeling framework using a distributed capacitive network. This framework self-consistently accounts for the interactions between the various components. We verify the functionality of the proposed model by simulating the proposed device, and show how it can capture the device characteristics.</p>

Nowadays, integrated circuits (IC) are mostly implemented using Complementary Metal Oxide Semiconductor (CMOS) transistor technology. This technology has allowed the chip industry to shrink transistors and thus increase the device density, circuit complexity, operation speed, and computation power of the ICs. However, in recent years, the scaling of transistor has faced multiple roadblocks, which will eventually lead the scaling to an end as it approaches physical and economic limits. The dominance of sub-threshold leakage, which slows down the scaling of threshold voltage VTH and the supply voltage VDD, has resulted in high power density on chips. Furthermore, even widely popular solutions such as parallel and multi-core computing have not been able to fully address that problem. These drawbacks have overshadowed the benefits of transistor scaling. With the dawn of Internet of Things (IoT) era, the chip industry needs adjustments towards ultra-low-power circuits and systems. In this thesis, energy-efficient Micro-/Nano-electromechanical (M/NEM) relays are introduced, their non-leaking property and abrupt switch ON/OFF characteristics are studied, and designs and applications in the implementation of ultra-low-power integrated circuits and systems are explored. The proposed designs compose of core building blocks for any functional microprocessor, for instance, fundamental logic gates; arithmetic adder circuits; sequential latch and flip-flop circuits; input/output (I/O) interface data converters, including an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC); system-level power management DC-DC converters and energy management power gating scheme. Another contribution of this thesis is the study of device non-ideality and variations in terms of functionality of circuits. We have thoroughly investigated energy-efficient approximate computing with non-ideal transistors and relays for the next generation of ultra-low-power VLSI systems.

<p>Energy efficient machine learning accelerator design</p>