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<P> The equilibrium behavior of the boundaries separating the a and y crystalline phases in the copper zinc alloy system is investigated by measuring the magnitude, the relative anisotropy and the temperature dependence of the interfacial energies. A model, consistent with the interfacial energetics, is proposed and supported by observations of misfit dislocations at the boundary. The migration kinetics of the y/β interface are determined for both dendritic and polyhedral morphologies and the atomic mechanisms of growth are inferred from the. internally faulted ordered y precipitates. </p> / Thesis / Doctor of Philosophy (PhD)

The continuously increasing demand for innovation in the miniaturization of microelectronics has driven the need for ever more precise fabrication strategies for device packaging, especially for printed circuit boards (PCBs). Subtractive copper etching is a fundamental step in the fabrication process, requiring very precise control of etch rate and etch factor. Changes in the etching chemical equilibrium have significant effects on etching behavior, and CuCl2 / HCl etching baths are typically monitored with several parameters including oxidation-reduction potential, conductivity, and specific gravity. However, the etch rate and etch factor can be difficult to control even under strict engineering controls of those monitoring parameters. The mechanism of acidic cupric chloride etching, regeneration and recovery is complex, and the current monitoring strategies can have difficulty controlling the interlocking chemical equilibria. A complimentary tool, thin-film UV-Vis spectroscopy, can be utilized to improve the current monitoring strategies, as UV-Vis is capable of identifying and predicting etching behavior that the current standard methodologies have difficulty predicting. Furthermore, as a chemically-sensitive probe, UV-Vis can investigate the complex changes to the chemical equilibrium and speciation of the etch bath, and can contribute overall to significant improvements in the control of the copper etching system in order to meet the demands of next-level design strategies.

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A plethora of novel scientific phenomena and practical applications, such as solid-state molecular solar cells and other optoelectronic devices for energy harvesting and lighting technologies, have catalyzed us to synthesize novel compounds with tunable properties. Synthetic routes, single crystal structures, and spectral and materials properties are described. Reactions of Ag(I) and Cu(I) precursors with various types of ligands -- including the azolates, diimines, and diiphosphines -- lead to the corresponding complexes in high yield. Varying the metal ions, ligands, synthetic methods, solvents, and/or stoichiometric ratio can change the properties including the molecular geometry or packing structure, reactivity, photophysical and photochemical properties, semiconducting behavior, and/or porosity of the functional coordination polymers obtained. For solar cells purposes, the absorption energy can be extended from the ultraviolet (UV) region, through the entire visible (Vis) region, onto a significant portion of the near-infrared (NIR) portion of the solar spectrum with high absorption coefficients due to the infinite conjugation of Cu(I) with diimine ligands. Twenty-eight crystal structures were obtained by conventional crystal growth methods from organic solvents, whereas their bulk product syntheses also included "green chemistry" approaches that precluded the use of hazardous organic solvents. The resulting products are characterized by powder x-ray diffraction (PXRD), Fourier transform infrared (FTIR), nuclear magnetic resonance (NMR), UV/Vis/NIR absorption/diffuse reflectance/photoluminescence spectroscopies, and thermogravimetric analysis (TGA). Regarding the scientific phenomena investigated, the highlighting work in this dissertation is the discovery of novel bonding/photophysical/optoelectronic properties of the following materials: a black absorber with absorption from 200- 900 nm, a very stable compound with a bright green luminescence obtained by a solventless reaction, and a novel coordination polymer showing uncommon interaction of Ag(I) with three different types of diimine ligands simultaneously.

Integrating nanometer-sized pores into low-k ILD films is one of the approaches to lower the RC signal delay and thus help sustain the continued scaling of microelectronic devices. While increasing porosity of porous dielectrics lowers the dielectric constant (k), it also creates many reliability and implementation issues. One of the problems is the little understood metal ion diffusion and drift in porous media. Here, we present a rigorous simulation method of Cu diffusion based on Master equation with elementary jump probabilities within the contiguous dielectric film, along the pore boundary, from the dielectric matrix to the pore boundary, and from the pore boundary to the matrix material. In view of the diffusional jump distance being as large as 2 nm, the nano-pores being on a similar length scale, and the film thickness being only a few tens of nanometers, the conventional diffusion equation in differential equation form is grossly inadequate and elementary jump frequencies are required for a proper description of the Cu diffusion in porous dielectric. The present atomistic approach allows a consistent implementation of Cu ion drift in electric field by lowering and raising of the diffusion barriers along the field direction. This will help understand the behavior of Cu interconnects under thermal or electric stress at an atomistic level. Another approach to lower the increasing RC delays is to bring memory and logic closer by integrating memory in the BEOL. Resistive RAM is one such memory is not transistor based and thus, does not require a silicon substrate. Thus, it offers the possibility of integration directly into the back-end reducing memory to logic distance from 1000s of µm to a 10s of nm. This 3D integration also allows for increased density as well. However, one barrier in the implementation of RRAM in the back end is the use of expensive as well as non-BEOL native material in conventional Cu/TaOx/Pt resistive devices. In this thesis, we present our research about functionality of RRAM with porous low-k dielectrics (which are a candidate for CMOS ILD), and through the similar elementary jump simulations, discuss the impact of porosity in dielectrics on the functionality of RRAM. Lastly, we present a cheaper replacement for Pt as the counter electrode in RRAM and show that it functions as good as Pt. This work addresses following three areas: 1. Modeling of diffusion in porous dielectrics through elementary jump based simulation. The model is based on random walk theory of elementary particle jumps. Initially, qualitative simulations are conducted without actual parameters. It is shown that Cu diffusion in porous dielectrics decreases quasi-linearly with porosity. Furthermore, it is shown that morphology of the pores may have a greater effect on diffusivity compared to porosity. The simulations are then calibrated with parameters, and the result is shown to yield a similar diffusivity times as actual process time. 2. Modeling of Cu ions drift in porous dielectrics under electric stress. First, the model is explained, and then qualitative simulation results are presented for porous dielectrics with varied porosities and morphologies. 3. Research to find a suitable replacement for Pt as the counter electrode in RRAM devices. The research methodology is discussed and a much cheaper Rh is selected as the potential replacement for Pt. Successful functionality of Rh based resistive devices is presented. / Master of Science / As electronic devices are being scaled for integrating more functions and higher computation, the internal delays are increasing, which may become a bottleneck in performance. To resolve this issue of internal delay, new materials are being proposed to replace the conventional materials to make the chip. One promising material like that are the porous dielectrics, to replace the conventional dielectrics used to manufacture electronic chips. The introduction of ‘air pores’ inside the dielectric used in chips may improve the delay, but it leads to several thermal and electrical reliability concerns. In this thesis, we argue that using differential equations to simulate effects on the nano-scale to explore such reliability issues is insufficient, and a simulation method based on individual atom/ion movement should be used to describe it. Here we provide a simulation model to explain the diffusivity of copper under thermal stress, as well as movement of Cu ions during electric stress in porous dielectrics, using our particle movement based simulation model, and prove that it delivers correct results. Secondly, the delay is especially significant for processor to memory communication. Thus, integrating memory close to processor is another method to reduce the delay. Resistive RAM (RRAM) is one such novel RAM technology that can be integrated close to processor. However due to usage of non-native as well as expensive materials, RRAM has not been commercially integrated close to processor. In this thesis, we also present a functioning RRAM using cheaper materials, as well as materials that are native to present electronics.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text