<p>The Particle Level set method is a successful extension to Level set methods to improve thevolume preservation in fluid simulations. This thesis will analyze how sparse volume data structures can be used to store both the signed distance function and the particles in order to improve access speed and memory efficiency. This Particle Level set implementation will be evaluated against Digital Domains current Particle Level set implementation. Different degrees of quantization will be used to implement particle representations with varying accuracy. These particles will be tested and both visual results and error measurments will be presented. The sparse volume data structures DB-Grid and Field3D will be evaluated in terms of speed and memory efficiency.</p>

<p>Xilinx Virtex II Pro FPGA with integrated PowerPC core offers an opportunity to implementing a software and hardware codesign. The software application executes on the PowerPC processor while the FPGA implementation of hardware cores coprocess with PowerPC to achieve the goals of acceleration. Another benefit of coprocessing with the hardware acceleration core is the release of processor load. This thesis demonstrates such an FPGA based software and hardware codesign by implementing a real time video processing project on Xilinx ML310 development platform which is featured with a Xilinx Virtex II Pro FPGA. The software part in this project performs video and memory interface task which includes image capture from camera, the store of image into on-board memory, and the display of image on a screen. The hardware coprocessing core does a contrast enhancement function on the input image. To ease the software development and make this project flexible for future extension, an Embedded Operating System MontaVista Linux is installed on the ML310 platform. Thus the software video interface application is developed using Linux programming method, for example the use of Video4Linux API. The last but not the least implementation topic is the software and hardware interface, which is the Linux device driver for the hardware core. This thesis report presents all the above topics of Operating System installation, video interface software development, contrast enhancement hardware implementation, and hardware core’s Linux device driver programming. After this, a measurement result is presented to show the performance of hardware acceleration and processor load reduction, by comparing to the results from a software implementation of the same contrast enhancement function. This is followed by a discussion chapter, including the performance analysis, current design’s limitations and proposals for improvements. This report is ended with an outlook from this master thesis.</p>

<p>Syftet med denna studie var att undersöka uppfattningarna hos karaktärsämneslärarna på gymnasiet med inriktning mot El-programmet, elektronik/datorteknik vad gäller de arbetsuppgifter som de utför inom karaktärsämnet, hur förberedda de menar sig vara för dessa uppgifter, samt i vad mån de anser sig behöva utveckla sin kompetens. Vidare var syftet att ta reda på vilken kompetensutveckling som erbjuds för dessa arbetsuppgifter. Studien bygger, utifrån frågeställningen i syftet, på en kvalitativ undersökning med hjälp av intervjuer. Intervjuerna genomfördes med sex karaktärsämneslärare inom avsedda program fördelat på fyra gymnasieskolor i fyra olika orter.</p><p>Resultatet visar att samtliga intervjuade känner sig kompetenta i sitt verksamma karaktärsområde i och med att de har både relevant utbildning och arbetslivserfarenhet. Men de flesta utför helst inte frivilligt det administrativa arbetet utan de vill ägna sin tid åt den tekniska delen som intresserar dem mest. Samtliga påstår att de även mer eller mindre saknar kompetens för administrativa arbetsuppgifter.</p><p>Alla respondenter anser att den snabba utvecklingen inom elektronik/datorteknik är huvudorsaken till att det krävs kompetensutveckling. Däremot anser de inte att de fått tillräckligt med erbjudande för en relevant kompetensutveckling. Detta på grund av olika saker, bland annat brist på pengar, tid, vikarier, etc.</p><p>Detta resultat indikerar även, enligt min uppfattning, vissa brister i skolväsendet i och med att samtliga respondenter har likadana åsikter om utförandet av vissa arbetsuppgifter.</p>

<p>The main issue of this thesis is making the behaviour model of Bluetooth EDR (enhanced data rate) baseband signal processing. This Bluetooth baseband project is part of the soft defined radio project at electrical engineering department, Linköping University.</p><p>In this project, both the basic rate and EDR model were built and simulated. The GFSK and π/4 DQPSK digital modulation and demodulation were implemented in C code. The BER was tested to evaluate the demodulation results. Furthermore, the error correction (FEC) and the error checking (HEC,CRC) were also implemented according to the Bluetooth standards. The CRC flag was detected to test the payload demodulation results.</p><p>Especially, GFSK and π/4 DQPSK specifications have to be combined with each other at sample rate of ADC.</p><p>Finally, the basic rate and EDR model were simulated to measure the BER and CRC performance.</p><p>From the simulation results, the receiver filter, synchronization and channel condition were three key points in this Bluetooth EDR system implementation.</p><p>So we get further understanding about the Bluetooth system specification and DSP implementation methods.</p>

<p>Implement a high-level model of computationally intensive part of 3D graphics pipe-line. Increasing popularity of handheld devices along with developments in hardware technology, 3D graphics on mobile devices is fast becoming a reality. Graphics processing is essentially complex and computationally demanding. In order to achieve scene realism and perception of motion, identifying and accelerating bottle necks is crucial. This thesis is about Open-GL graphics pipe-line in general. Software which implements computationally intensive part of graphics pipe-line is built. In essence a rasterization unit that gets triangles with 2D screen, texture co-ordinates and color. Triangles go through scan conversion, texturing and a set of other per-fragment operations before getting displayed on screen.</p>

<p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p>

<p>The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures.</p><p>This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply.</p><p>It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control.</p> / Report code: LiU-TEK-LIC-2006:36.

<p>Space-Time Adaptive Processing (STAP) has been widely used in modern radar systems such as Ground Moving Target Indication (GMTI) systems in order to suppress jamming and interference. However, the high performance comes at a price of higher computational complexity, which requires extensive powerful hardware.</p><p>The new STI Cell Broadband Engine (CBE) processor combines PowerPC core augmented with eight streamlined high-performance SIMD processing engine offers an opportunity to implement the STAP baseband signal processing without any full custom hardware. This paper presents the implementation of an STAP baseband signal processing flow on the state-of-the-art STI CELL multiprocessor, which enables the concept of Software-Defined Radar (SDR). The potential of the Cell BE processor is studied so that kernel subroutine such as QR decomposition, Fast Fourier Transform (FFT), and FIR filtering of STAP are mapped to the SPE co-processors of Cell BE processor with variety of architectural specific optimization techniques.</p><p>This report starts with an overview of airborne radar technique and then the standard, specifically the third-order Doppler-factored STAP are introduced. Next, it goes with the thorough description of Cell BE architecture, its programming tool chain and parallel programming methods for Cell BE. In later chapter, how the STAP is implemented on the Cell BE processor is discussed and the simulation results are presented. Furthermore, based on the result of earlier benchmarking, an optimized task partition and scheduling method is proposed to improve the overall performance.</p>

<p>Much functionality of today's vehicles runs as software on embedded computer systems. This includes, for example, automatic climate control and engine control.</p><p>As the processors necessarily are located in diffent physical locations inside the vehicle wires must be drawn between processors that need to communicate. Therefore, it is typical to have one or several buses connecting the processors in an embedded computer network, thus creating a distributed system. As some parts of the system in the car have real-time properties, it is necessary to validate that the real-time properties are upheld in the distributed system.</p><p>This thesis presents the design and implementation of an adaptive cruise controller (ACC), which is a cruise controller that also keeps a minimum distance to the closest vehicle in front. Further, the performance of the ACC has been evaluated using an existing system-level simulator for distributed real-time systems together with metrics for Quality-of-Control (QoC).</p><p>The ACC has then been simulated under different scenarios. The scenarios include outside conditions, for example the slope of the road, the behaviour of the vehicle in front, and the desired velocity, as well as internal conditions as adding different amounts of extra load on the processors and the bus.</p><p>The results show that the functionality of the ACC starts deteriorating when the extra load on the nodes reaches high levels. When the extra load reaches very high levels, the ACC stops functioning completely. The results also show that the extra load on the bus has very little effect on the performance of the ACC.</p>

<p>Integrated systems become larger and more complicated every day while time to market is shortened. Due to this, there is a need for flexible hardware platforms that use programmable logic not only for custom hardware but also for realizing embedded processors.</p><p>This thesis aims to select a suitable, FPGA targeted, soft processor core and adapt the real-time operating system OSE_ck to run on the selected target. A study of possibilities to integrate setup and configuration of OSE_ck into the processor’s IDE is also performed.</p><p>Studies of OSE_ck and the two processor candidates MicroBlaze and Nios II have been performed. The processor study showed that MicroBlaze and Nios II have a very similar architecture and both are suitable to host OSE_ck. MicroBlaze was chosen as target processor mainly because of more available documentation regarding operating system integration.</p><p>Performance and footprint was measured with OSE_ck on MicroBlaze. The performance figures indicate that MicroBlaze can not be expected to have the same processing power as hard processors but works well as a control processor. To achieve high application performance, custom hardware accelerators can be connected. Integration investigations and tests have been performed with the goal of making an interface that conforms to the normal MicroBlaze design flow.</p><p>OSE_ck has been successfully adapted to run on MicroBlaze and integration in the development environment is possible although some steps have to be done manually. Alternative integration options are discussed.</p>