The conversion of audio from the digital to analog domain has the potential to result in distortion due to converter overload. This occurs because some peaks in the signal cannot be defined digitally and only become problematic during the conversion into the analog domain, exceeding the level that can be represented by the converter, causing it to overload. Although True Peak limiting and metering can prevent and monitor this issue, some professional mastering engineers choose not to do so. The study tested claims made against overload prevention, including the adequacy of headroom in modern D/A converters and the inaudibility of the distortion caused by overload. Preference was also added to the audibility claim. Measurements show that there is not enough headroom in modern D/A converters to avoid overload, but the distortion created by overload is generally inaudible in an uncompressed WAVE format hard rock song. Additionally, there is no clear preference. The measurements found that overload only occurs when the device's volume is raised to its maximum output.

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Power electronics is inevitably concerned with the processing of variable speed power generations such as in wind turbines, aircraft systems and naval on-board ship systems. The nature of these types of energy is distinct in that their frequency and power vary depending on the speed of the prime-mover. To make use of the variable speed energy, a power processing scheme which transforms the variable speed energy into a constant frequency power is required. There are measures such as mechanical and electrical links for such purposes. Electrical link systems are chosen in this study due to their fast responses and high reliabilities. The power conversion stage may be a dc link with a line-commutated converter, a dc link with a self-commutated inverter, or a cycloconverter. The line-commutated converter and cycloconverter power stages require a fixed frequency supply for operation whereas the self-commutated inverter is capable of stand-alone operation, thus making it attractive. Two cases of variable speed power generation using a permanent magnet synchronous machine (hereafter referred to as PMSM) and a switched reluctance machine (hereafter referred to as SRM) were studied in this dissertation. The possible use of PMSMs has been proved by the good correlation between the experimental results and the theoretically predicted results. Three different control strategies have been proposed, implemented in hardware, and experimentally verified. The efficiency of the VSCF power conversion with a self commutated converter were comparable to the one using a line-commutated converter. A novel converter topology with no dc link capacitor has been proposed for the application of SRMs to the VSCF power conversion. The proposed topology directly links the constant frequency ac source to the SRM. This feature enhances the reliability of the power conversion scheme and reduces the weight and volume of the system. The correlation between the theoretical and experimental results of some key issues showed the feasibility of the proposed VSCF power conversion scheme. In the course of the study, one stage ac to dc power conversion with a compact transformer was required for dc loads. However, phase-controlled ac to dc conversion has the disadvantages of low power factor and harmonic pollution on the utility side, particularly in the case where dc voltage regulation is required. Therefore, a novel single phase rectifier for dc load which provides ohmic isolation with a high frequency transformer is extensively investigated. The proposed scheme had a wide output variation on dc output while maintaining unity power factor and sinusoidal current in the ac input side. Three control strategies for the operation of the converter were proposed and verified experimentally. The harmonic spectra on ac and dc sides are analytically derived and experimentally proved under some load conditions. / Ph. D.

Graduation date: 1996

Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clockless transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

Today&amp / #8217 / s analog modulators and upconverters are inadequate to synthesize and modulate signals with high &amp / #8216 / Spurious Free Dynamic Range&amp / #8217 / (SFDR). Thus, the main objective of this thesis is to design and implement a &amp / #8216 / Digital Signal Synthesizer&amp / #8217 / (DSS) that is capable of synthesizing signals between 50-100 MHz with 60dB SFDR and to modulate them variable symbol rates and modulation techniques with very high phase/frequency resolution and switching speed while keeping the amplitude modulation occurring during a modulated symbol duration as small as possible. In this thesis, digital words of the desired signals are first synthesized in a &amp / #8216 / Field Programmable Gate Array&amp / #8217 / (FPGA) using &amp / #8216 / Direct Digital Synthesizer&amp / #8217 / (DDS) fundamentals and then converted to analog signals with a high speed &amp / #8216 / Digital to Analog Converter&amp / #8217 / (DAC). In order to attain the analog requirements, the system variables such as DAC analog performance, nonlinearities, sample and hold affects, DDS parameters, system clock, bandwidth requirements of analog filters and how they effect the output performance are studied. FPGA blocks that are capable of modulating and synthesizing desired signals are designed and programmed on a FPGA. Finally, single tone and modulated signals are synthesized with this DSS implementation and measured in order to verify this system&amp / #8217 / s performance and capabilities.