This work presents the bottom-up fabrication of DNA origami-assembled metal nanowires and metal-semiconductor junctions, and their electrical characterization. Integration of metal and semiconductor nanomaterials into prescribed sites on self-assembled DNA origami has facilitated the fabrication of electronic nanomaterials, whereas use of conventional tools in their characterization combines bottom-up and top-down technologies. To expand the contemporary DNA-based nanofabrication into nanoelectronics, I performed site-specific metallization of DNA origami to create arbitrarily arranged gold nanostructures. I reported improved yields and conductivity measurements for Au nanowires created on DNA origami tile substrates. I measured the conductivity of C-shaped Au nanowires created on DNA tiles (∼130 nm long, 10 nm diameter, and 40 nm spacing between measurement points) with a four-point measurement technique which revealed the resistivity of the gold nanowires was as low as 4.24 × 10-5 Ω m. Next, I fabricated DNA origami-templated metal-semiconductor junctions and performed electrical characterization. Au and Te nanorods were attached to DNA origami in an alternating fashion. Electroless gold plating was used to create nanoscale metal--semiconductor interfaces by filling the gaps between Au and Te nanorods. Two-point electrical characterization indicated that the Au--Te--Au junctions were electrically connected, with non-linear current--voltage curves. Finally, I formed metal-semiconductor nanowires on DNA origami by annealing polymer-encased nanorods. Polymer-coated Au and Te nanorods pre-attached to ribbon-shaped DNA origami were annealed at 170°C for 2 min. Gold migration occurred onto Te nanorods during annealing and established electrically continuous interfaces to give Au/Te nanowires. Electrical characterization of these Au/Te/Au assemblies revealed both nonlinear current-voltage curves and linear plots that are explained. The creation of electronic nanomaterials such as metal nanowires and metal-semiconductor junctions on DNA origami with multiple techniques advances DNA nanofabrication as a promising path toward future bottom-up fabrication of nanoelectronics.

Bottom-up self-assembly has the potential to fabricate nanostructures with advanced electrical features. DNA templates have been used to enable such self-assembling methods due to their versatility and compatibility with various nanomaterials. This dissertation describes research to advance several different steps of biotemplated nanofabrication, from DNA assembly to characterization. I assembled different nanomaterials including surfactant-coated Au nanorods, DNA-linked Au nanorods and Pd nanoparticles on DNA nanotubes ~10 micrometer long, and on ~400 nm long bar-shaped DNA origami templates. I optimized seeding by changing the surfactant and magnesium ion concentrations in the seeding solution. After successful seeding, I performed electroless plating on those nanostructures to fabricate continuous nanowires. Using the four-point probe technique, I performed resistivity measurements for Au nanowires on DNA nanotubes and obtained values between 9.3 x 10-6 and 1.2 x 10-3 ohm meter. Finally, I demonstrated the directed placement of DNA origami using block copolymer self-assembly. I created a gold nanodot array using block copolymer patterning and metal evaporation followed by lift-off. Then, I used different ligand groups and DNA hybridization to attach DNA origami to the nanodots. The DNA hybridization approach showed greater DNA attachment to Au nanodots than localization by electrostatic interaction. These results represent vital progress in understanding DNA-templated components, nanomaterials, and block copolymer nanolithography. The work in this dissertation shows potential for creating DNA-templated nanodevices and their placement in an ordered array in future nanoelectronics. Each of the described materials and techniques further has potential for addressing the need for increased complexity and integration for future applications.

DNA origami templates have been studied due the versatility of shapes that can be designed and their compatibility with various materials. This has potential for future electronic applications. This work presents studies performed on the electrical properties of DNA origami templated gold nanowires. Using a DNA origami tile, gold nanowires are site specifically attached in a “C” shape, and with the use of electron beam induced deposition of metal, electrically characterized. These wires are electrically conductive with resistivities as low as 4.24 x 10-5 Ω-m. During moderate temperature processing nanowires formed on DNA origami templates are shown to be affected by the high surface mobility of metal atoms. Annealing studies of DNA origami gold nanowires are conducted, evaluating the effects of atom surface mobility at various temperatures. It is shown that the nanowires separate into individual islands at temperatures as low as 180° C. This work shows that with the use of a polymer template the temperature at which island formation occurs can be raised to 210° C. This could allow for post processing techniques that would otherwise not be possible.

The nano-contact spin torque oscillator (NC-STO) is an emerging device for highly tunable microwave frequency generation in the range from 0.1 GHz to above 65 GHz with an on-chip footprint on the scale of a few μm. The frequency is inherent to the magnetic material of the NC-STO and is excited by an electrical DC current by means of the spin torque transfer effect. Although the general operation is well understood, more detailed aspects such as a generally nonlinear frequency versus current relationship, mode-jumping and high device-to-device variability represent open questions. Further application-oriented questions are related to increasing the electrical output power through synchronization of multiple NC-STOs and integration with CMOS integrated circuits. This thesis consists of an experimental part and a simulation part. Experimentally, for the frequency stability it is found that the slow but strong 1/f-type frequency fluctuations are related to the degree of nonlinearity and the presence of perturbing, unexcited modes. It is also found that the NC-STO can exhibit up to three propagating spin wave oscillation modes with different frequencies and can randomly jump between them. These findings were made possible through the development of a specialized microwave time-domain measurement circuit. Another instrumental achievement was made with synchrotron X-rays, where we image dynamically the magnetic internals of an operating NC-STO device and reveal a spin wave mode structure with a complexity significantly higher than the one predicted by the present theory. In the simulations, we are able to reproduce the nonlinear current dependence by including spin wave-reflecting barriers in the nm-thick metallic, magnetic free layer. A physical model for the barriers is introduced in the form of metal grain boundaries with reduced magnetic exchange coupling. Using the experimentally measured average grain size of 30 nm, the spin wave mode structure resulting from the grain model is able to reproduce the experimentally found device nonlinearity and high device-to-device variability. In conclusion, the results point out microscopic material grains in the metallic free layer as the reason behind the nonlinear frequency versus current behavior and multiple propagating spin wave modes and thereby as a source of device-to-device variability and frequency instability. / Dagens snabba utveckling inom informationsteknik drivs på av ständigt växande informationsmängder och deras samhällsanvändning inom allt från resursoptimering till underhållning. Utvecklingen möjliggörs till stor del hårdvarumässigt av miniatyrisering och integrering av elektroniska komponenter samt trådlös kommunikation med allt större bandbredd och högre överföringshastighet. Det senare uppnås främst genom utnyttjande av högre radiofrekvenser i teknologiskt tidigare oåtkomliga delar av spektrumet. Frekvensutnyttjandet har det senaste årtiondet ökat markant i mikrovågsområdet med typiska frekvenser runt 2.4 GHz och 5.2-5.8 GHz. I den spinntroniska oscillatorn (STO:n) möjliggörs frekvensgenerering i det breda området från 0.1 GHz upp till över 65 GHz av en komponent med mikrometerstorlek som kan integreras direkt i CMOS-mikrochip. Till skillnad från i konventionella radiokretsar med oscillatorer konstruerade av integrerade transistorer och spolar, genereras mikrovågsfrekvensen direkt i STO:ns magnetiska material och omvandlas därefter till en elektrisk signal genom komponentens magnetoresistans. Dessa materialegenskaper möjliggör ett tillgängligt frekvensband med extrem bredd i en och samma STO, som därtill kan frekvensmoduleras direkt genom sin styrström och på så sätt förenklar konstruktionen av sändarsystem. STO:ns icke-linjära egenskaper kan potentiellt också användas för att i en och samma komponent blanda ned mottagna mikrovågssignaler och på så sätt förenkla konstruktionen även av mikrovågsmottagare. STO:ns signalegenskaper bestäms av det magnetiska materialets fysik i form av magnetiseringsdynamik driven av elektriskt genererade spinnströmmar. I denna avhandling studeras denna dynamik experimentellt med särskilt fokus på frekvensstabiliteten i den hittills mest stabila STO-typen; nanokontakts-STO:n. Genom mätningar i tidsdomän av STO:ns elektriska signaler runt 25 GHz har frekvensstabiliteten funnits hänga samman med den typ av icke-linjärt beteende som också funnits vara utmärkande för tillverkningsvariationen i komponenterna. Mikroskopiska undersökningar av materialet visar att en trolig källa till denna variation är den magnetiska metallens uppbyggnad i form av korn i storleksordningen 30 nm, och datorsimuleringar av en sådan materialstruktur har visats kunna reproducera de experimentella resultaten. Därtill har en metod utvecklats för att med röntgenstrålning direkt mäta de små, magnetiska mikrovågsrörelserna i materialet. Denna röntgenteknik möjliggör detaljerade experimentella studier av magnetiseringsdynamiken och kan användas för att verifiera och vidareutveckla den existerande teorin för mikrovågsspinntronik. Sammantaget förs STO-teknologin genom denna studie ett steg närmare sina tänkbara samhällsbreda tillämpningar inom snabb, trådlös kommunikation för massproducerade produkter med integrerad sensor- och datorfunktionalitet. / <p>QC 20160620</p>

L'intégration de diélectriques High-k dans les empilements de grille des transistors a fait naître des problèmes de fiabilité complexes. A cela vient s'ajouter, en vue des technologies sub-32nm planaires, de nouvelles problématiques liées à l'utilisation de substrats silicium sur isolant complètement désertés FDSOI. En effet, l'intégration d'un oxyde enterré sous le film de silicium non seulement va modifier l'électrostatique de la structure mais aussi introduire une nouvelle interface Si/SiO2 sujette à d'éventuelles dégradations. Ce manuscrit présente différentes méthodes de caractérisation électrique ainsi que différentes études de fiabilité des dispositifs FDSOI intégrants des empilements High-&#954;/ grille métallique. Dans un premier temps, une étude complète du couplage électrostatique dans des structures FDSOI est réalisée, permettant de mieux appréhender l'effet d'une tension en face arrière sur les caractéristiques électriques des dispositifs. Différentes méthodes de caractérisation des pièges d'interface sont ensuite présentées et adaptées, quand cela est possible, au cas spécifique du FDSOI, où les défauts entre le film de silicium et l'oxyde enterré doivent être pris en compte. Enfin, différentes études de fiabilité sont présentées, des phénomènes de PBTI et de NBTI sur des dispositifs à canaux longs aux phénomènes propres aux dispositifs de petite dimension, tels que l'impact des porteurs chauds dans des structures FDSOI à film ultra fins et les effets parasites d'augmentation de la tension de seuil lorsque les largeurs des transistors diminuent. / The integration of High-k dielectrics in recent CMOS technologies lead to new complex reliability issues. Furthermore new concerns appear with the use of fully depleted silicon on insulator (FDSOI) substrates for future sub-32nm planar technologies. Indeed, the integration of a buried oxide underneath the silicon film changes the electrostatic of the structure and create a new Si/SiO2 interface which may be degraded. This thesis presents different electrical characterization techniques and reliability studies on High-&#954;/metal gate FDSOI transistors. First, a complete electrostatic study of FDSOI structures is done allowing a better understanding of the effects of backgate biases. Different techniques to characterize interface traps are then presented and adapted to FDSOI devices, where traps at the silicon film/buried oxide interface must be considered. Finally, different reliability studies are presented; from NBTI and PBTI issues on long channel devices to specific concerns related to small gate length transistors such as hot carriers degradation on ultra-thin film FDSOI devices and threshold voltage increase with gate width scaling.

Ce travail de thèse porte sur l'intégration de matériaux de haute constante diélectrique (High-k) en tant que diélectrique interpoly dans les mémoires non volatiles de type Flash. L'objectif est de déterminer quel matériaux High-k seraient des candidats probables au remplacement de l'empilement ONO utilisé en tant que diélectrique interpoly. Une gamme de matériaux high-k ont été étudiés via des caractérisations électriques (I-V, C-V, statistique de claquage…) et physiques (TEM, EDX, XPS…) afin d'éliminer les matériaux ne répondant pas au cahier des charges d'un diélectrique interpoly. Les difficultés et les obstacles liés a l'intégration de matériaux High-k dans une chaine de procédés de fabrication de mémoires Flash ont été pris en compte, et des solutions ont été proposées. / The work of this thesis is on integration of high dielectric constant materials (High-k) as dielectric interpoly in Flash non volatile memories. The objective is to determine which High-k materials are suitable as interpoly dielectric in place of the ONO stack currently used. A range of High-k materials have been studied by electrical characterizations (I-V, C-V, breakdown statistics…) and physical characterizations (TEM, EDX, XPS…) in order to select those with the best properties for an interpoly dielectric. The difficulties in integration of High-k materials in a Flash memory process flow have been taken in account and solutions have been proposed.

In Cu(In,Ga)Se2 (CIGS) solar cells the CIGS layer serves as the light absorber, growing naturally p-type. Together with an n-type buffer layer they form a p-n heterojunction. Typically, CdS is used as a buffer, although other, less toxic materials are investigated as alternatives. The intrinsic p-type doping of CIGS layers is the result of complex defect physics. Defect formation energies in CIGS are very low or even negative, which results in extremely high defect concentrations. This leads to many unusual electrical phenomena that can be observed in CIGS devices. This thesis mostly focuses on three of these phenomena: light-soaking, light-on-bias, and light-enhanced reverse breakdown. Light-soaking is a treatment that involves illuminating the investigated device for an extended period of time. In most CIGS solar cells it results in an improvement of open-circuit voltage, fill factor, and efficiency that can persist for hours, if not days. The interplay between light-soaking and the remaining two phenomena was studied. It was found that light-soaking has a strong effect on light-on-bias behavior, while the results for light-enhanced breakdown were inconclusive, suggesting little to no impact. Light-on-bias is a treatment which combines simultaneous illumination and application of reverse bias to the studied sample. Illuminating CdS-based samples with red light while applying a reverse bias results in a significant increase in capacitance due to filling of traps. In many cases, this is accompanied by a decrease in device performance under red illumination. Complete recovery is possible by illuminating the treated sample with blue light, which causes hole injection from the CdS buffer. In samples with alternative buffer layers, there is little distinction between red and blue illumination, and the increase in capacitance is milder. At the same time, there is little effect on device performance. Reverse breakdown can occur when a sufficiently large reverse bias is applied to a p-n junction, causing a large reverse current to flow through the device. In CIGS solar cells, the voltage at which breakdown occurs in darkness decreases in the presence of blue illumination. A model explaining the breakdown in darkness was proposed as a part of this thesis. The model assumes that all voltage drops on the buffer layer in darkness and on the CIGS layer under blue illumination. The high electric field in the buffer facilitates Poole-Frenkel conduction and Fowler-Nordheim tunneling between the absorber and the buffer.

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

Avec l'évolution des technologies et le développement des objets connectés, la consommation des circuits est devenue un sujet important. Dans cette thèse nous nous concentrons sur la consommation des mémoires non volatiles à piégeage de charge. Afin de diminuer la consommation, différentes architectures ont vu le jour comme les mémoires 2T ou Split Gate. Nous proposons deux nouvelles architectures de mémoires permettant la diminution de la consommation par rapport à une mémoire Flash standard. La première, appelée ATW (Asymmetrical Tunnel Window), est composée d'une marche d'oxyde au niveau de son oxyde tunnel qui lui permet d'être moins consommatrice qu'une mémoire Flash standard. Une seconde architecture mémoire appelée eSTM (embedded Select Trench Memory) est aussi présentée. Son principal atout est la présence de son transistor de sélection qui est indispensable pour avoir une faible consommation. Grâce à son architecture, cette cellule est bien meilleure que l'architecture proposée précédemment (ATW). Une dernière étude a été réalisée afin d'optimiser le procédé de fabrication de la mémoire eSTM pour le rendre plus robuste. / With the evolution of technologies and the development of connected objects, the circuit consumption is becoming an important subject. In this thesis, we focus on the consumption of trap-charge non-volatile memories. To decrease the consumption, different architectures have emerged, like 2T or Split Gate memories. We propose two new memory architectures allowing to decrease the consumption compared to the standard Flash memory. The first, called ATW (Asymmetrical Tunnel Window), is composed of an oxide step in the tunnel oxide which allows to be less consumer than a standard Flash memory. A second memory architecture called eSTM (embedded Select Trench Memory) is also presented. Its main advantage is its select transistor which is essential to obtain a lower consumption. Thanks to its architecture, this cell is better than the previously proposed architecture (ATW). The last study has been performed to optimize the process flow of the eSTM memory to make it more robust.

Neste trabalho, foram caracterizados eletricamente capacitores MOS com alumina (Al2O3) e aluminato de háfnio (AlxHf1-xOy) como dielétricos de porta, além disso, estes filmes dielétricos foram caracterizados fisicamente. A alumina foi obtida da oxidação anódica de filmes de alumínio evaporados sobre p-Si (100) através de imersão em ácido nítrico por 4 ou 6 min, para diferentes etapas de limpeza finais do substrato: solução diluída de ácido fluorídrico (DHF) ou solução de peróxido sulfúrico (SPM). Análises de retroespalhamento de Rutherford (RBS), espectroscopia por dispersão em energia (EDS) e espectroscopia por dispersão de comprimento de onda (WDS) indicam a formação da alumina estequiométrica, sendo que a difração de raios-X (XRD), mostrou o caráter amorfo do dielétrico. Por intermédio de curvas capacitância x tensão (CV) foram obtidas a espessura equivalente ao óxido de silício (EOT2,8nm), a densidade de estados de interface (Dit1,4x1011ev-1cm-2) e a permissividade elétrica da alumina (high-k10,6). A admitância associada à corrente de fuga em capacitores MOS foi modelada através de emissão por Frenkel-Poole, tunelamento por Fowler-Nordheim e/ou corrente de fuga constante. Os aluminatos de háfnio (AlxHf1-xOy) foram obtidos sobre p-Si (100), através de deposição atômica por camadas (ALD) para diferentes proporções molares de háfnio (25, 50 ou 75%) e para diferentes tratamentos posteriores (1000ºC, 60s em N2 ou N2+O2 ou laser). A espessura e a rugosidade foram obtidas com a ajuda da técnica de reflectometria de raios-X (XRR). A proporção molar de háfnio adotada no processo de obtenção dos filmes foi confirmada através de análises RBS e WDS. Por XRD, foi verificado o caráter amorfo e a separação de fases nos aluminatos e, por espalhamento de raios-X em ângulo-rasante e pequena abertura (GISAXS), foram analisadas as novas fases formadas. Por fim, da análise CV, foram obtidos EOT9,54nm, resistência série (Rs68,3) e a permissividade elétrica para o aluminato de háfnio (high-k15,2). Finalmente, uma modelagem da admitância associada à corrente de fuga em função da frequência foi proposta para as estruturas MOS. / In this work, MOS capacitors were electrically characterized using alumina (Al2O3) and hafnium aluminate (AlxHf1-xOy) as gate dielectrics; also, the same dielectrics films were physically characterized. Anodic alumina was obtained from oxidation of evaporated aluminum films immersed in nitric acid for 4 or 6 min for different last step cleanings of the p-Si (100) substrates: diluted hydrofluoric acid (DHF) or sulfur peroxide mixture (SPM). Rutherford Backscattering (RBS), Energy Dispersive Spectroscopy (EDS) and Wavelength Dispersive Spectroscopy (WDS) have shown the formation of stoichiometric alumina and the dielectric amorphous structure was revealed by X-Ray Diffraction (XRD). From Capacitance x Voltage curves (CV), it was obtained the equivalent oxide thickness (EOT2.8nm), interface trap density (Dit1.4x1011ev-1cm-2) and Al2O3 dielectric constant (high-k10.6). The admittance that represents the leakage process was modeled according to Frenkel-Poole emission, Fowler-Nordheim tunneling and/or constant leakage admittance. Hafnium aluminates (AlxHf1-xOy) were obtained on (100) silicon wafer surfaces by Atomic Layer Deposition (ALD) for different hafnium molar ratios (25, 50 or 75%) and for different treatments (1000ºC, 60s in N2 or N2+O2 or laser). Thickness and roughness were extracted from X-Ray Reflectometry (XRR) spectra. The hafnium molar ratios used in ALD process were confirmed by RBS and WDS. XRD analysis was used to establish the amorphous structure and phase separation in the aluminates after thermal treatments and Grazing-Incidence Small-Angle X-Ray Scattering (GISAXS) was used to analyze the new phases formed. From CV analysis, it was extracted EOT9.54nm, series resistance (Rs68.3) and dielectric constant from hafnium aluminate (high-k15.2). Finally, the admittance that represents the leakage was modeled in function of the frequency for the MOS structures.