The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications. Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study. A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications. Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed. Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated. Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis. The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.

L’intégration des oscillateurs dans les microcontrôleurs est aujourd’hui un enjeu industriel majeur suscitant une forte concurrence entre les principaux acteurs du marché. En effet, les oscillateurs sinusoïdaux sont des circuits indispensables, et sont majoritairement basés sur l’utilisation d’un résonateur à quartz ou MEMS externe. De plus en plus d’investigations sont menées afin d’intégrer des dispositifs résonants dans les boîtiers et éviter ainsi toutes les contraintes extérieures limitant les performances de l’oscillateur. En ce sens, nous avons étudié dans ce travail le comportement électrique, et notamment inductif, des liaisons filaires permettant de connecter une puce à son boîtier de protection. L’avantage d’utiliser ce composant passif est principalement son faible coût. Ce composant a été caractérisé en utilisant plusieurs méthodologies de modélisations et de mesures sur une large plage fréquentielle. Cette étude propose un modèle permettant aux concepteurs d’utiliser une caractéristique électrique équivalente dans une technologie CMOS standard. L’intégration du composant dans une cellule résonante est démontrée au sein d’un prototype. / Nowadays, the integration of oscillators into microcontrollers is a major industrial challenge which involves a large competition between the main actors of this market. Indeed, sine wave oscillators are essential circuits, and are fore the most part based on external crystal or MEMs resonators. More and more investigations are carried out in order to integrate the resonant structure into the package, and avoid all external constraints able to restrict the performances of the oscillator. With this in mind, we studied in this work the electrical behavior, in particular the inductive behavior of bond wires which are electrical connections between a die and its package. The main advantage to use this type of component is its low cost of manufacturing. This passive component has been characterized using several measurement tools on a wide range of frequencies. A RLC model has been presented, allowing analogue designers to use an electrical equivalent circuit in standard CMOS technology. The integration of the passive component in a resonant cell has been demonstrated in a prototype.

Este trabalho apresenta o estudo do desempenho analógico do transistor SOI MOSFET com tensão de limiar dinamicamente variável (DTMOS). Esse dispositivo é fabricado em tecnologia SOI parcialmente depletado (PD). A tensão de limiar desta estrutura varia dinamicamente porque a porta do transistor está curto-circuitada com o canal do mesmo, melhorando significativamente suas características elétricas quando comparadas aos transistores PD SOI MOSFET convencionais. Entre as características principais desse dispositivo, pode-se citar a inclinação de sublimiar praticamente ideal (60 mV/dec), devido ao reduzido efeito de corpo, resultando num aumento significativo da corrente total que corresponde à soma da corrente do transistor principal com a corrente do transistor bipolar parasitário inerente à estrutura. Diversas simulações numéricas bidimensionais, utilizando o simulador ATLAS, foram executadas a fim de se obter um melhor entendimento do dispositivo DTMOS, quando comparado com o SOI convencional. As características elétricas analisadas através da simulação numérica bidimensional apresentam a corrente de dreno em função da polarização da porta considerando VD baixo e alto (25 mV e 1V). O canal teve uma variação de 1 até 0,15 µm. Através dessas simulações foram obtidos as principais características elétricas e parâmetros analógicos para estudo do DTMOS em comparação com o SOI convencional como: transcondutância (gm), tensão de limiar (VTH), inclinação de sublimiar (S). Considerando a polarização de dreno em 1V foi obtido a transcondutância e a inclinação de sublimiar. Na etapa seguinte foi feito simulações para obter as curvas características de IDS x VDS, onde a tensão aplicada na porta variou de 0 a 200 mV (VGT), onde se obteve a tensão Early (VEA), a condutância de saída (gD) dos dispositivos, bem como o ganho intrínseco de tensão DC (AV) e a freqüência de ganho unitário (fT). Os resultados experimentais foram realizados em duas etapas: na primeira, extraíram-se todas as curvas variando o comprimento do canal (L) de 10 à 0,15 µm e na segunda, manteve-se um valor fixo do comprimento do canal (10 µm), variando somente a largura do canal (W) entre 10 e 0,8 µm, para identificar quais seriam os impactos nos resultados. A relação da transcondutância pela corrente de dreno do DTMOS foi 40 V-1 na média, independentemente do comprimento do canal e observou-se um aumento de 14 dB no ganho intrínseco quando usado o comprimento de canal de 0,22 µm, em comparação com SOI convencional. Foi verificado uma melhora na performance dos parâmetros analógicos do DTMOS quando comparado com o PDSOI e têm sido muito utilizado em aplicações de baixa tensão e baixa potência. / This work presents the study of analog performance parameters of PDSOI (Partially-depleted) transistor in comparison with a Dynamic Threshold MOS transistor (DTMOS). The DTMOS is a partially-depleted device with dynamic threshold voltage. This variation of threshold voltage is obtained when the gate is connected to the silicon film (channel) of the PDSOI device, improving the electrical characteristics of a conventional SOI. The characteristics of this device is an ideal subthreshold slope (60mV/dec), due to the reduced body effect and improved current drive. When the gate voltage increases in DTMOS (body tied to gate), there is a body potential increase, which results in a higher drain current due to the sum of the MOS current with the bipolar transistor (BJT) one. Several two-dimensional numerical simulations were done with the ATLAS Simulator to obtain a better knowledge of DTMOS device to compare with PDSOI. The electrical characteristics analyzed through two-dimensional numerical simulations are the drain current as a function of (VGS) with drain bias fixed at 25 mV and 1 V. The channel length varied from 10 to 1 um. Through these simulations the main electrical characteristics and the analog performance parameters were obtained of DTMOS in comparison with conventional SOI, as: transconductance (gm), threshold (VTH) voltage, and subthreshold slope (S). Considering the drain bias of 1V, transconductance and subthreshold voltage were obtained. In the next step, the characteristics curves of drain current (IDS) as a function of (VDS), where the gate bias varied from 0 to 200 mV of (VGT), to obtain the Early voltage (VEA) and output conductance (gD), the intrinsic gain DC (AV) and a unit-gain frequency to both devices were simulated. The experimental results were measured in two steps: in the first step all electrical characteristics and parameters considering a channel length (L) variation were obtained and in the second step a channel length was fixed and varied the width (W) was varied to study if this variation had any effects on the results. The gm/IDS ratio of DTMOS was 40 V-1 , independent of channel length and a increase of 14 dB in intrinsic gain, when using a channel length of 0,22 µm, compared with the conventional SOI was obtained. Improvement was observed in the performance of analog parameters when compared whit conventional SOI and DTMOS has been widely used in Low-Power- Low-Voltage applications.

Ce travail de thèse porte sur l’élaboration de matériaux polymères conjugués absorbants dans le proche infra-rouge. Il est issu du projet TAPIR financé par l’ANR dans lequel nous visons le développement de dispositifs d’interface Homme/Machine (IHM) pour des applications dans le secteur de la santé, afin de limiter la propagation des agents pathogènes. Les IHM étant contrôlées avec la main, sans contact, grâce à la réflectivité de la peau, (gamme spectrale 850-950 nm), il faut développer des matériaux absorbant dans cette gamme. Dans ce projet, notre rôle a été de synthétiser la partie active du photodétecteur infrarouge utilisé pour récupérer l’information. Une étude bibliographique et des calculs préliminaires ont permis une sélection judicieuse de différents monomères afin d’assurer une stabilité intrinsèque et obtenir les propriétés d’absorption requises. Différents monomères donneurs (D) et accepteurs (A) ont été combinés afin de synthétiser des copolymères alternés de types (D-A). Deux familles de copolymères absorbants dans le proche infrarouge ont ainsi été synthétisés Tous les copolymères ont été synthétisés via la polycondensation Stille. Leurs propriétés optiques, électroniques et leurs stabilités thermiques ont été étudiées. Par la suite, après avoir confirmé le rôle prépondérant de la force du monomère accepteur, par rapport à celle du donneur, sur les propriétés d’absorptions et les niveaux électroniques des différents copolymères obtenus, nous avons développé une approche originale très peu rapportée dans la littérature. Elle consiste en l’élaboration de copolymères de type (A-A). Ainsi, nous avons synthétisé six copolymères absorbants dans la gamme de longueurs d’onde souhaitée, et même au-delà. Enfin, certains copolymères ont pu être caractérisés en dispositifs OFET et photodétecteurs. / This thesis work focuses on the development of conjugated polymeric materials which absorb in the near infrared. It is the result of the TAPIR project funded by the ANR in which we aim to develop human-machine interface (HMI) devices for applications in the health sector, in order to limit the spread of pathogens. Since HMIs are controlled by hand, without contact, thanks to the reflectivity of the skin (spectral range 850-950 nm), it is necessary to develop materials which ansorb in this range. In this project, our role was to synthesize the active part of the infrared photodetector used to retrieve the information. A bibliographical study and preliminary calculations have allowed a judicious selection of different monomers to ensure intrinsic stability and obtain the required absorption properties. Different donor monomers (D) and acceptors (A) were combined to synthesize alternating copolymers of types (D-A). Two families of copolymers which absorb in the near infrared have been synthesized. All copolymers have been synthesized via Stille polycondensation. Their optical, electronic and thermal properties have been studied. Subsequently, after confirming the predominant role of the strength of the accepting monomer, compared to that of the donor, on the absorption properties and electronic levels of the various copolymers obtained, we developed an original approach that has been reported very rarely in the literature. It consists of the production of copolymers of the type (A-A). Thus, we have synthesized six copolymers which absorb in the desired wavelength range, and even beyond. Finally, some copolymers have been characterized as OFET devices and photodetectors.

Este trabalho apresenta o estudo do desempenho analógico do transistor SOI MOSFET com tensão de limiar dinamicamente variável (DTMOS). Esse dispositivo é fabricado em tecnologia SOI parcialmente depletado (PD). A tensão de limiar desta estrutura varia dinamicamente porque a porta do transistor está curto-circuitada com o canal do mesmo, melhorando significativamente suas características elétricas quando comparadas aos transistores PD SOI MOSFET convencionais. Entre as características principais desse dispositivo, pode-se citar a inclinação de sublimiar praticamente ideal (60 mV/dec), devido ao reduzido efeito de corpo, resultando num aumento significativo da corrente total que corresponde à soma da corrente do transistor principal com a corrente do transistor bipolar parasitário inerente à estrutura. Diversas simulações numéricas bidimensionais, utilizando o simulador ATLAS, foram executadas a fim de se obter um melhor entendimento do dispositivo DTMOS, quando comparado com o SOI convencional. As características elétricas analisadas através da simulação numérica bidimensional apresentam a corrente de dreno em função da polarização da porta considerando VD baixo e alto (25 mV e 1V). O canal teve uma variação de 1 até 0,15 µm. Através dessas simulações foram obtidos as principais características elétricas e parâmetros analógicos para estudo do DTMOS em comparação com o SOI convencional como: transcondutância (gm), tensão de limiar (VTH), inclinação de sublimiar (S). Considerando a polarização de dreno em 1V foi obtido a transcondutância e a inclinação de sublimiar. Na etapa seguinte foi feito simulações para obter as curvas características de IDS x VDS, onde a tensão aplicada na porta variou de 0 a 200 mV (VGT), onde se obteve a tensão Early (VEA), a condutância de saída (gD) dos dispositivos, bem como o ganho intrínseco de tensão DC (AV) e a freqüência de ganho unitário (fT). Os resultados experimentais foram realizados em duas etapas: na primeira, extraíram-se todas as curvas variando o comprimento do canal (L) de 10 à 0,15 µm e na segunda, manteve-se um valor fixo do comprimento do canal (10 µm), variando somente a largura do canal (W) entre 10 e 0,8 µm, para identificar quais seriam os impactos nos resultados. A relação da transcondutância pela corrente de dreno do DTMOS foi 40 V-1 na média, independentemente do comprimento do canal e observou-se um aumento de 14 dB no ganho intrínseco quando usado o comprimento de canal de 0,22 µm, em comparação com SOI convencional. Foi verificado uma melhora na performance dos parâmetros analógicos do DTMOS quando comparado com o PDSOI e têm sido muito utilizado em aplicações de baixa tensão e baixa potência. / This work presents the study of analog performance parameters of PDSOI (Partially-depleted) transistor in comparison with a Dynamic Threshold MOS transistor (DTMOS). The DTMOS is a partially-depleted device with dynamic threshold voltage. This variation of threshold voltage is obtained when the gate is connected to the silicon film (channel) of the PDSOI device, improving the electrical characteristics of a conventional SOI. The characteristics of this device is an ideal subthreshold slope (60mV/dec), due to the reduced body effect and improved current drive. When the gate voltage increases in DTMOS (body tied to gate), there is a body potential increase, which results in a higher drain current due to the sum of the MOS current with the bipolar transistor (BJT) one. Several two-dimensional numerical simulations were done with the ATLAS Simulator to obtain a better knowledge of DTMOS device to compare with PDSOI. The electrical characteristics analyzed through two-dimensional numerical simulations are the drain current as a function of (VGS) with drain bias fixed at 25 mV and 1 V. The channel length varied from 10 to 1 um. Through these simulations the main electrical characteristics and the analog performance parameters were obtained of DTMOS in comparison with conventional SOI, as: transconductance (gm), threshold (VTH) voltage, and subthreshold slope (S). Considering the drain bias of 1V, transconductance and subthreshold voltage were obtained. In the next step, the characteristics curves of drain current (IDS) as a function of (VDS), where the gate bias varied from 0 to 200 mV of (VGT), to obtain the Early voltage (VEA) and output conductance (gD), the intrinsic gain DC (AV) and a unit-gain frequency to both devices were simulated. The experimental results were measured in two steps: in the first step all electrical characteristics and parameters considering a channel length (L) variation were obtained and in the second step a channel length was fixed and varied the width (W) was varied to study if this variation had any effects on the results. The gm/IDS ratio of DTMOS was 40 V-1 , independent of channel length and a increase of 14 dB in intrinsic gain, when using a channel length of 0,22 µm, compared with the conventional SOI was obtained. Improvement was observed in the performance of analog parameters when compared whit conventional SOI and DTMOS has been widely used in Low-Power- Low-Voltage applications.

Neste trabalho é apresentado o desenvolvimento de um sistema de ensaios elétricos de dispositivos de emissão de campo para que, a partir desses ensaios, possam ser extraídas as características elétricas desses dispositivos. O sistema é composto por hardware e software dedicados e pode ser controlado local ou remotamente. O hardware inclui uma fonte de alta tensão gerenciada por um sistema microcontrolado. Para programação do microcontrolador, foi utilizado um ambiente de programação disponibilizado pelo próprio fabricante do microcontrolador. Nesse desenvolvimento foram empregados periféricos de entrada e saída do microcontrolador, tais como: leitura de teclado, manipulação de USART, ajuste do nível de saída da fonte e conversores analógicos digitais. No microcontrolador foram implantadas rotinas de configuração, personalização e varredura do display, além de envio e recebimento de informações com um computador. Para o computador foi elaborado um programa dedicado para a manipulação do sistema de ensaio utilizando o conceito de instrumentação virtual, que permite escolher o tipo de ensaio elétrico, armazenar as leituras dos ensaios e a visualização \"on-line\" do andamento do ensaio através de diversos gráficos disponíveis no programa, inclusive o gráfico de Fowler-Nordheim, adequado para o estudo de dispositivos de emissão de campo. / At this work is presented the development of a field emission devices trial system to render possible to obtain the electrical characteristics of the field emission devices. Here are shown some results taken from some trials. During the development of the trial system, it was used at the programming microcontroller stage, the environment of programming supplied by the manufacturer of the microcontroller. At this development, peripheral of input and output from the microcontroller, like, keyboard reading, USART manipulation, SPI manipulation and analogic to digital converters were used. At the microcontroller were implanted routines of configuration, customing and display sweeping, besides the transmission and the receiving of instructions came from the computer. For computer, a program was elaborated dedicated for manipulation of the trials system applying the virtual instrumentation concept, storing readings of the trials as well as the visualization \"on-line\" of the course of the trial through available graphs in the program. As an important result of this work has the establishment of a system for trial of field emission devices controlled on place or remotely, system that is composed by hardware and software in which were made several trials with acquisition and data manipulation and the presentation of received information.

Actuellement, la majorité des composants à semi-conducteur pour l'électronique de puissance est réalisée à partir de silicium. Afin de répondre aux nouvelles contraintes électriques et thermiques imposées par la montée en tension et en densité de puissance des convertisseurs d'énergie électrique, une solution repose sur l'emploi d'un semi-conducteur à large bande interdite tel que le carbure de silicium (SiC), du fait de son champ électrique critique (EC) environ dix fois plus élevé que celui du silicium et de sa capacité à fonctionner à des températures supérieures à 200 °C. Une revue des nombreuses publications concernant des diodes en SiC de tenue en tension élevée, voire leur disponibilité commerciale (jusqu'à 10 kV), est présentée, qui montre les progrès réalisés grâce aux efforts portés sur l'amélioration du matériau et l'optimisation de la protection périphérique des composants. L'étape de passivation primaire reste une étape critique très souvent mentionnée. Beaucoup moins de travaux prennent en considération l'impact des matériaux de passivation secondaire et d'encapsulation. L'objectif de cette thèse est de contribuer à une meilleure connaissance des paramètres et des mécanismes de rupture impactant la tenue en tension à l'état bloqué de l'ensemble que forment la puce et son l'environnement isolant électrique. Ainsi, une étude expérimentale de l'influence de différents paramètres liés au semi-conducteur ainsi qu'aux matériaux de passivation et d'encapsulation présents en surface de la puce a été menée, à l'aide de diodes en SiC-4H avec protection périphérique par poche implantée, réalisées par la société IBS, dans le cadre du projet de recherche 'FilSiC'. Dans un premier temps, une étude par simulation numérique de l'ensemble de la structure (SiC, électrodes métalliques, isolants) a été effectuée à l'aide du logiciel Sentaurus Device (Synopsys). Elle a permis de quantifier les contraintes en champ électrique dans toute la structure pour une tension appliquée donnée, et leur sensibilité aux caractéristiques des matériaux isolants prises en compte. Cette étude a également servi au choix des paramètres liés au substrat épitaxié et à la géométrie latérale et en surface des diodes (les paramètres technologiques étant fixés par ailleurs), pertinents pour l'étude expérimentale de leur tension de rupture, dans une gamme de 1 kV à 6 kV. En parallèle, la caractérisation électrique, au sein de structures Métal-Isolant-Semi-conducteur, du matériau de passivation primaire utilisé (dépôt épais de dioxyde de silicium), dans une gamme de température jusqu'à 300 °C, a permis de déterminer ses propriétés électriques, dont la rigidité diélectrique. Le travail a ensuite porté sur la caractérisation à température ambiante de la tension de rupture de la structure complète des différentes diodes fabriquées, effectuée sous vide et sous azote à la pression atmosphérique. Les comportements expérimentaux visualisés sous vide au moment du claquage, et couplés aux informations issues des simulations, ont notamment permis d'estimer les valeurs des champs maximaux induits dans les différents matériaux isolants, et de corréler leur impact avec les valeurs de rigidité diélectrique connues pour ces isolants. Les résultats complémentaires sous azote ont permis de confirmer certains paramètres technologiques et mécanismes mis en jeu lors du claquage des diodes d'autre part. Plusieurs conclusions utiles pour l'optimisation des paramètres technologiques (épitaxie et poche) et des couches isolantes de passivation et d'encapsulation (épaisseur, permittivité) de la diode 'haute tension' en SiC ont pu être dégagées de ces travaux. / Nowadays, most of the semiconductor devices used in power electronics are silicon (Si) based devices. In order to meet the new electrical and thermal constraints induced by the demand in rising both the operating voltage and the power density of the electrical energy converters, the use of wide band gap semiconductors such as silicon carbide (SiC) may represent an adequate solution, thanks to their critical electric field (EC) which is about ten times higher than that of Si and to their ability of operating at temperatures beyond 200 °C. A state-of-the-art on the readily (commercially) available high voltage SiC diodes (10kV or higher) is presented, highlighting the progress made in improving the materials themselves as well as their peripheral protection. However, regarding the die insulating materials, the studies mainly focus on the primary passivation step, which was often mentioned as the most critical one. Obviously much less work is carried out on the impact of the secondary passivation and encapsulation materials. The goal of this study is to contribute to a better knowledge of the mechanisms involved in the SiC chips and electrically insulating environment breakdown while in a blocking state, as well as to the identification of the most relevant parameters acting on these phenomena. Thus, a study of the correlated properties of the semiconductor and the passivation and encapsulation materials present on the surface of the chip was carried out on SiC-4H bipolar diodes protected by junction termination extension (JTE), supplied by IBS society, within the framework of the 'FilSiC' research project. First, a numerical simulation study of the entire structure (SiC and insulating materials) was carried out using the Sentaurus Device software (Synopsys). This allowed for quantifying the electric field stresses throughout the structure for a given applied voltage as well as their dependence on the properties of the considered insulating materials. This study was equally used for choosing the appropriate parameters of the epitaxial substrate and for designing the lateral and the surface geometry of the diodes (the technological parameters being fixed elsewhere), in view of the subsequent experimental study of their breakdown voltage in the 1kV-6kV range. Concurrently, the electrical characterization of the primary passivation material used (thick silicon dioxide layer) was performed by using MIS (metal-insulator-semiconductor) type structures, in a temperature range of up to 300 °C. This allowed to determine its main electrical properties, particularly the dielectric breakdown voltage. The work then focused on the room-temperature characterization of the breakdown voltage of the full structures built around the different manufactured diodes. The tests were carried out both under high vacuum conditions and under nitrogen at atmospheric pressure. The behavior of the different study cases observed under vacuum conditions during the breakdown, coupled with the simulation results, allowed to determine the values of the maximum electric fields induced in the different insulating materials and to correlate them to their known dielectric breakdown values. On the other hand, additional results obtained under nitrogen atmosphere confirmed some technological parameters and mechanisms at play during the breakdown of the diodes. Several guidelines for the optimization of these technological parameters (epitaxy and JTE) and of the insulating passivation and encapsulation layers (thickness, permittivity) of the "high voltage" SiC diode were derived from this study.

Neste trabalho é apresentado o desenvolvimento de um sistema de ensaios elétricos de dispositivos de emissão de campo para que, a partir desses ensaios, possam ser extraídas as características elétricas desses dispositivos. O sistema é composto por hardware e software dedicados e pode ser controlado local ou remotamente. O hardware inclui uma fonte de alta tensão gerenciada por um sistema microcontrolado. Para programação do microcontrolador, foi utilizado um ambiente de programação disponibilizado pelo próprio fabricante do microcontrolador. Nesse desenvolvimento foram empregados periféricos de entrada e saída do microcontrolador, tais como: leitura de teclado, manipulação de USART, ajuste do nível de saída da fonte e conversores analógicos digitais. No microcontrolador foram implantadas rotinas de configuração, personalização e varredura do display, além de envio e recebimento de informações com um computador. Para o computador foi elaborado um programa dedicado para a manipulação do sistema de ensaio utilizando o conceito de instrumentação virtual, que permite escolher o tipo de ensaio elétrico, armazenar as leituras dos ensaios e a visualização \"on-line\" do andamento do ensaio através de diversos gráficos disponíveis no programa, inclusive o gráfico de Fowler-Nordheim, adequado para o estudo de dispositivos de emissão de campo. / At this work is presented the development of a field emission devices trial system to render possible to obtain the electrical characteristics of the field emission devices. Here are shown some results taken from some trials. During the development of the trial system, it was used at the programming microcontroller stage, the environment of programming supplied by the manufacturer of the microcontroller. At this development, peripheral of input and output from the microcontroller, like, keyboard reading, USART manipulation, SPI manipulation and analogic to digital converters were used. At the microcontroller were implanted routines of configuration, customing and display sweeping, besides the transmission and the receiving of instructions came from the computer. For computer, a program was elaborated dedicated for manipulation of the trials system applying the virtual instrumentation concept, storing readings of the trials as well as the visualization \"on-line\" of the course of the trial through available graphs in the program. As an important result of this work has the establishment of a system for trial of field emission devices controlled on place or remotely, system that is composed by hardware and software in which were made several trials with acquisition and data manipulation and the presentation of received information.

La réduction des dimensions des dispositifs MOSFET devient de plus en plus complexe a réalisé, et les nouvelles technologies MOSFET se confrontent à de fortes difficultés. Pour surmonter ce problème, une nouvelle technique, appelée intégration 3D VLSI, est étudiée : remplacer la structure plane conventionnelle par un empilement vertical de transistors.En particulier, l’intégration 3D séquentielle ou CoolCube™ au CEA-Leti permet de profiter pleinement de la troisième dimension en fabriquant séquentiellement les transistors. La réalisation d’une telle intégration apporte une nouvelle contrainte, celle de fabriquer le transistor du dessus avec un budget thermique faible (inférieur à 500°C), afin de préserver les performances du transistor d'en dessous. Puisque ce budget thermique est principalement influencé par l'activation des dopants, plusieurs techniques innovatrices sont actuellement investiguées au CEA-LETI, afin de fabriquer le drain et la source. Dans ce manuscrit, nous utiliserons la recristallisation en phase solide comme mécanisme pour activer les dopants (inférieures à 600 °C). L’objectif de cette thèse est donc de fabriquer et de caractériser des transistors dont l’activation des dopants est réalisée grâce à ce mécanisme, afin d’atteindre des performances similaires à des transistors réalisés avec un budget thermique standard. Ce travail est organisé autour de l’activation des dopants, et en trois chapitres, où chaque chapitre est spécifique à une intégration (« Extension Last »/ « Extension First », « Gate Last »/ « Gate First ») et à une architecture (FDSOI, FINFET) considérées. Ces chapitre permettront, grâce aux caractérisations électriques, morphologiques et aux simulations, de développer un procédé de recristallisation stable à 500°C, à la fois pour les nMOS et les pMOS, et de proposer de nouveaux schémas d’intégrations, afin de réaliser des transistors à faible budget thermique et compatibles avec l’intégration 3D Séquentielle. / The down scaling of MOSFET device is becoming harder and the development of future generation of MOSFET technology is facing some strong difficulties. To overcome this issue, the vertical stacking of MOSFET in replacement of the conventional planar structure is currently investigated. This technique, called 3D VLSI integration, attracts a lot of attention, in research and in the industry. Indeed, this sequential stacking of transistor enables to gain in density and performance without reducing transistors dimensions.More specifically, 3D sequential integration or CoolCube™ at CEA-Leti enables to fully benefit of the third dimension by sequentially manufacturing transistors. Implementing such an integration provides the new constraint of manufacturing top transistor with low thermal budget (below 500°C) in order to preserve bottom-transistor performances. As most of the thermal budget is due to the dopant activation, several innovative techniques are currently investigated at CEA-LETI.In this work, solid phase epitaxy regrowth will be used as the mechanism to activate dopants below 600°C. The aim of this thesis is thus to manufacture and to characterize transistors with low-temperature dopant activation, in order to reach the same performance as devices manufactured with standard thermal budget. The work is organized around the dopant activation, and in three chapters, according to each considered integration scheme (Extension Last/ Extension First, Gate Last/ Gate First) and architecture (FDSOI, FINFET). These chapters, assisted by relevant simulations, electrical and morphological characterizations, will enable to develop a new and stable 500°C recrystallization process for both N and P FETs, and to propose new integration schemes in order to manufacture transistors with low thermal budget and compatible with the 3D sequential integration.

A deeper understanding of Cu(In,Ga)Se2 (CIGS) solar cells is important for the further improvement of these devices. This thesis is focused on the use of electrical modelling as a tool for pursuing this aim. Finished devices and individual layers are characterized and the acquired data are used as input in the simulations. Band gap gradients are accounted for when modelling the devices. The thesis is divided into two main parts. One part that treats the influence of cadmium free buffer layers, mainly atomic layer deposited (Zn,Mg)O, on devices and another part in which the result of CIGS absorber layer modifications is studied. Recombination analysis indicates that interface recombination is limitting the open circuit voltage (Voc) in cells with ZnO buffer layers. This recombination path becomes less important when magnesium is introduced into the ZnO giving a positive conduction band offset (CBO) towards the CIGS absorber layer. Light induced persistent photoconductivity (PPC) is demonstrated in (Zn,Mg)O thin films. Device modelling shows that the measured PPC, coupled with a high density of acceptors in the buffer-absorber interface region, can explain light induced metastable efficiency improvement in CIGS solar cells with (Zn,Mg)O buffer layers. It is shown that a thin indium rich layer closest to the buffer does not give any significant impact on the performance of devices dominated by recombination in the CIGS layer. In our cells with CdS buffer the diffusion length in the CIGS layer is the main limitting factor. A thinner CIGS layer improves Voc by reducing recombination. However, for thin enough absorber layers Voc deteriorates due to recombination at the back contact. Interface recombination is a problem in thin devices with Zn(O,S) buffer layers. This recombination path is overshadowed in cells of standard thickness by recombination in the CIGS bulk. Thin cells with Zn(O,S) buffer layers have a higher efficiency than CdS cells with the same absorber thickness.