Currently, wide bandgap semiconductor devices feature increased efficiency, higher current handling capabilities, and higher reverse blocking voltages than silicon devices while recent fabrication advances have them drawing near to the marketplace. However these new semiconductors are in need of new packaging that will allow for their application in several important uses including hybrid electrical vehicles, new and existing energy sources, and increased efficiency in multiple new and existing technologies. Also, current power module designs for silicon devices are rife with problems that must be enhanced to improve reliability. This thesis introduces new packaging that is thermally resilient and has reduced mechanical stress from temperature rise that also provides increased circuit lifetime and greater reliability for continued use to 300°C which is within operation ratings of these new semiconductors. The new module is also without problematic wirebonds that lead to a majority of traditional module failures which also introduce parasitic inductance and increase thermal resistance. Resultantly, the module also features a severely reduced form factor in mass and volume.

With increased focus on miniaturization and high performance in electronics, thermal management is a very important area of research today. In multiple applications such as portable electronics, consumer electronics, military applications, automobile, power electronics, high performance computing, etc. innovative thermal management strategies are necessary. In this work, two novel approaches to dissipate redundant heat better- first by novel carbonaceous-nanoparticle additives to develop thermal interface materials with superior performance and the second by using advanced metal additive manufacturing techniques to design and analyze metal-lattice based heat sinks are presented. Thermal Interface Materials with multiple carbon-based nanoparticle fillers such as coal-derived Multi Layered Graphene (MLG), standard reduced Graphene Oxide (rGO), Multi-Walled Carbon Nano Tubes (MWCNTs), and Graphene Nano-Platelets (GNPs) in thermal paste were synthesized and seen to have superior heat dissipation properties. Also, graphene was synthesized from coal through an in-house, facile, scalable and cost-effective process. The enhancement in thermal conductance varies from ~70% in the coal-MLG to ~14% in MWCNTs-based TIMs. Noteworthy is ~3.5 times larger enhancement in thermal performance with the in-house coal-derived-MLG as compared to the commercially available g-MLG. At a 3% wt. fraction of coal-MLG, enhancement in thermal conductance was almost 120% higher compared to the base thermal grease. In the second part, metal lattice-based heat sinks are designed for additive manufacturing for use in passive cooling of high-flux thermal management. A parametric optimization based on the lattice geometry, thickness, and height subject to additive manufacturing constraints is conducted. Intricate metal lattices with low mass based on the Simple Cubic, Octet, and Voronoi structures were generated by implicit modelling in nTopology® and their thermal performance was analyzed through numerical analysis using commercial CFD packages. The Voronoi lattice performed best with a significant improvement in thermal performance (~18% reduction in junction temperature difference with respect to ambient) as compared to a standard baseline Longitudinal heat Sink (LHS), while reducing the mass of the heat sink by ~2.1 times. Such optimized metal lattice-based heat sinks can lead to significant downsizing, reduction in overall mass and cost in applications where thermal management is critical with a need for low mass. We believe that such novel scalable materials and processes suited for mass production could be critical in meeting the material, design and product development needs to tackle the thermal management challenges of the future. / Master of Science / With increase in demand of high power and performance in electronics, there is a concurrent increase in redundant heat that needs to be dissipated. With enhanced focus and push towards electric vehicles, defense, consumer electronics, datacenter and supercomputing applications, electronics cooling is a critical area of research today. There are two primary resistances to heat- as it is removed from electronics package to the surrounding atmosphere – due to the thin layer of a material called Thermal Interface Material (TIM) at the interface between the heat sink and the package, and the resistance offered by the heat sink itself. In this work, a two-pronged approach for better cooling in electronics is presented. Firstly, carbon-based nano-sized particles are used to synthesize novel TIMs that provide superior heat transport capabilities as compared to a standard baseline. In the second approach, complex metal-lattice based heat sinks are designed for manufacturing with advanced techniques such as metal 3D printing. Multiple carbon-based nano-particle additives such as Multi Layered Graphene synthesized from coal (MLG), standard commercially available reduced Graphene Oxide (rGO), Multi-Walled Carbon Nano Tubes (MWCNTs), and Graphene Nano-Platelets (GNPs) are dispersed in thermal paste and all of the resulting composites were found to remove heat better from electronics packages. The improvement in this ability varies from ~70% in the coal-MLG to ~14% in MWCNTs-based TIMs. Noteworthy is ~3.5 times larger enhancement in the heat transport ability with the use of in-house coal-derived-MLG as compared to the commercially available g-MLG. At an 3% wt. fraction of coal-MLG, there was a 1.2x increase in thermal performance as compared to the base thermal grease. Also, it is significant to mention that MLG was synthesized from coal through an in-house, facile scalable and cost-effective process. In the second part, metal lattice-based heat sinks designed for metal 3D printing for use in passive cooling of electronics was investigated. Multiple geometric parameters such as the lattice type, thickness, and height subject to additive manufacturing constraints were studied. Intricate metal lattices with low mass based on three structures- Simple Cubic, Octet, and Voronoi were generated by implicit modelling, and their thermal performance was predicted by computer based-simulations using commercial CFD packages. The Voronoi lattice performed best with a significant reduction (~18%) in junction temperature difference with the surrounding atmosphere- as compared to a standard baseline rectangular heat sink design, while simultaneously reducing the mass of the heat sink by ~2.1 times. Such optimized metal lattice-based heat sinks can lead to significant reduction in overall mass, size, and cost in weight sensitive applications. We believe that such novel scalable materials, designs, and processes suited for mass production could be critical in meeting the material, design and product development needs to tackle the thermal management challenges of the near future.

L'utilisation du diamant comme composant d'électronique de puissance est une perspective intéressante tant en ce qui concerne les applications hautes température que forte puissance. La problématique principale de ces travaux réalisés dans le cadre du programme Diamonix, réside dans l'étude et l'élaboration d'un packaging permettant la mise en oeuvre d'une puce diamant devant fonctionner à des températures variant entre -50°C et 300°C. Nous nous sommes intéressés au choix des matériaux de connexion de la puce avec son environnement. Suite à l'étude bibliographique, nous proposons différentes solutions de matériaux envisageables pour le substrat métallisé, les brasures et les métallisations. Dans un second temps, les différents éléments ont été réalisés puis caractérisés à partir d'essais de nanoindentation et de nanorayage. Des essais mécaniques ont permis de caractériser le comportement élastoviscoplastique et l'endommagement des brasures. Ces derniers essais ont servi de base expérimentale à l'identification des paramètres d'un modèle de comportement viscoplastique couplé avec l'endommagement et qui a été spécialement élaboré pour cette étude. Le modèle de comportement a été implémenté dans un code de calcul par éléments finis via une sous-routine. Il permet notamment de simuler le processus de dégradation d'un assemblage. Enfin, ce modèle de comportement a été mis en oeuvre dans des modélisations thermomécaniques de différentes configurations de véhicules test. / Use of diamond as constitutive component in power electronics devices is an interesting prospect for the high temperature and high power applications. The main challenge of this research work included in the Diamonix program is the study and the elaboration of a single-crystal diamond substrate with electronic quality and its associated packaging. The designed packaging has to resist to temperatures varying between -50°C and 300°C. We contributed to the choice of the connection materials intended to be used in the final test vehicle and which can handle such temperature gaps. In the first part, we present a state-of-the-art of the various materials solutions for extreme temperatures. Following this study, we propose a set of materials which considered as potential candidates for high temperature packaging. Special focus is given for the most critical elements in power electronic assemblies which are metallizations and solders. Once the materials choice carried out, thin substrate metallizations, solders and DBC coatings are studied using nanoindentation and nanoscratch tests. Mechanical tests were also carried out on solders to study their elastoviscoplastic and damage behavior. The experimental results are used as database for the identification of the parameters of the viscoplastic model coupled with a porous damage law, worked out for the case of solders. The behavior model is implemented as a user subroutine UMAT in a FE code to predict the degradation of a 2D power electronic assembly and various materials configuration for a 3D test vehicle.

Reliability and sensitive information protection are critical aspects of integrated circuits. A novel technique using near-field evanescent wave coupling from two subwavelength gratings (SWGs), with the input laser source delivered through an optical fiber is presented for tamper evidence of electronic components. The first grating of the pair of coupled subwavelength gratings (CSWGs) was milled directly on the output facet of the silica fiber using focused ion beam (FIB) etching. The second grating was patterned using e-beam lithography and etched into a glass substrate using reactive ion etching (RIE). The slightest intrusion attempt would separate the CSWGs and eliminate near-field coupling between the gratings. Tampering, therefore, would become evident. Computer simulations guided the design for optimal operation of the security solution. The physical dimensions of the SWGs, i.e. period and thickness, were optimized, for a 650 nm illuminating wavelength. The optimal dimensions resulted in a 560 nm grating period for the first grating etched in the silica optical fiber and 420 nm for the second grating etched in borosilicate glass. The incident light beam had a half-width at half-maximum (HWHM) of at least 7 µm to allow discernible higher transmission orders, and a HWHM of 28 µm for minimum noise. The minimum number of individual grating lines present on the optical fiber facet was identified as 15 lines. Grating rotation due to the cylindrical geometry of the fiber resulted in a rotation of the far-field pattern, corresponding to the rotation angle of moiré fringes. With the goal of later adding authentication to tamper evidence, the concept of CSWGs signature was also modeled by introducing random and planned variations in the glass grating. The fiber was placed on a stage supported by a nanomanipulator, which permitted three-dimensional displacement while maintaining the fiber tip normal to the surface of the glass substrate. A 650 nm diode laser was fixed to a translation mount that transmitted the light source through the optical fiber, and the output intensity was measured using a silicon photodiode. The evanescent wave coupling output results for the CSWGs were measured and compared to the simulation results.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are favored for their smaller specific on-resistance, lower switching losses, and higher theoretical temperature limits as compared to traditional silicon (Si) power switches. They have the potential to dramatically increase the power density and efficiency of power electronics systems by replacing traditional Si-based switches. However, GaN HEMTs have a faster switching speed compared to their Si-based counterparts. Minimizing the parasitic loop inductances of the GaN HEMT package is crucial for reducing electromagnetic interference (EMI) noise and voltage spikes. Another concern with GaN HEMTs comes from their lower thermal conductivity and smaller die size. The HEMTs generally have a higher heat flux density, and accordingly, demand better heat dissipation. Thus, innovations are needed for making GaN HEMT packages with low parasitic inductances and higher thermal performances to further their applications in high-frequency, high-power-density converters. To reduce loop inductance, other researchers have embedded GaN HEMTs in a printed circuit board (PCB) and used plated vias for interconnections and heat dissipation. However, this approach requires more complex manufacturing steps and has lower thermal performance. This dissertation introduces different embedded packaging techniques for 650V, 150A GaN HEMTs; this method involves interconnecting the bare chips between direct-bonded copper (DBC) and a PCB or between two DBCs, as discussed in Chapter 2. Vertical interconnections by gold pins and silver rods are introduced and implemented in embedded packages to limit the parasitic loop inductance within 1.5 nH and parasitic resistances within 1.5 mΩ. The thermal performance of the embedded GaN HEMT packages is experimentally verified in Chapter 2; then, the junction-to-case thermal resistance (RthJC) measurement is discussed in Chapter 3. The common temperature-sensitive electrical parameters (TSEPs) of a GaN HEMT for junction temperature measurement lack sufficient sensitivity or stability due to the electron-trapping effect. The non-uniform distribution of the case temperature and a large temperature gradient between the case and heatsink also make it difficult to accurately measure the case temperature. In Chapter 3, gate-to-gate resistance (Rg2g) is selected as the TSEP for junction temperature measurement. The stacked thermal interface material (TIM) technique was used to reduce errors in case temperature measurement. This technique was implemented in a custom GaN HEMT package and in embedded GaN HEMT packages for measuring junction-to-case thermal resistance. The discrepancy between measurement and simulation is less than 20%, and the junction-to-case thermal resistance for embedded packages is within 0.1 °C/W. Chapter 4 evaluates the reliability of the GaN HEMT embedded packages developed in Chapter 2 by utilizing a power cycling test. Monitoring the junction temperature of the embedded packages online is challenging during the power cycling test. Other approaches have used the on-resistance as the TSEP in order to monitor junction temperature for GaN HEMTs but this is not accurate due to electron trapping. As discussed in Chapter 3, Rg2g is chosen as the TSEP to monitor the junction temperature without worrying about the influence of electron trapping, and this approach cycles the embedded packages at 75 A from 25°C to 125°C. The packages can endure 23,000 power cycles before failure. This work is the first to develop, fabricate, and characterize embedded packages for 650V, 150A GaN HEMT bare chips. These embedded packages with high-power-rated GaN HEMT bare dice provide an opportunity to reduce the number of paralleled power switches, reduce the system's cooling size, and increase the system's power density. In addition, this work is the first to develop the junction-to-case thermal resistance measurement technique by gate-to-gate electrical resistance and stacked-TIM for GaN HEMT packages. The technique helps enable solid thermal design for power electronics systems. / Doctor of Philosophy / Power switches are everywhere in our daily life. They are the fundamental elements in power converters for converting power to electric vehicles. As global power demand for these applications continues to increase, high levels of both efficiency and power density are crucial for power switches. However, traditional silicon-based switches are already very mature, and their properties are very close to their theoretical limits. For further improvement, researchers have tried to replace traditional Si switches with wide-bandgap switches, which have much higher theoretical limits. Gallium nitride high-electron-mobility transistors (GaN HEMTs) are one of the candidates. However, packaging these switches (GaN HEMTs) is challenging due to their initial properties. They naturally switch very quickly and have smaller sizes compared to traditional Si-based switches. The fast switching speed brings high dv/dt and di/dt during the switching period. It causes voltage spikes and electromagnetic interference (EMI) issues. And the smaller size contributes to higher heat flux density, thus requiring more efficient heat dissipation. To solve the challenge of packaging GaN HEMTs, this dissertation has developed embedded packaging techniques to achieve quiet switching and good heat dissipation. These packaging techniques enable GaN HEMTs' advantages and increase the power density and efficiency of power electronics systems. To experimentally verify the thermal performance of the embedded packages developed a junction-to-case thermal resistance measurement technique was introduced. The thermal resistance of a custom GaN HEMT package was measured, as were those of the embedded packages CPES also developed. The simulation results and the experimental results are close to each other. Finally, to further evaluate whether or not the newly developed embedded packages are reliable, power cycling tests were carried out at I = 75 A. The packages survived over 23,000 cycles before failure.

Le besoin pressant de substitution du plomb dans les alliages de soudure a conduit à une introduction très rapide de nouveaux alliages sans plomb dont la connaissance en termes de comportement n'est pas assez approfondie. En effet, d'autres problématiques sont apparues (l'augmentation de la température du procédé de soudage, trop grand choix disponible dans les alliages alternatifs) alors que les problèmes relatifs aux alliages actuels sont restés sans réponse (le changement incessant de la microstructure des alliages de soudure, la méthodologie empirique prédisant la durée de vie). Tous les paramètres cités ci-dessus modifient la stabilité et la fiabilité des performances spécifiques de l'alliage de soudure et par conséquence, de tout le module électronique.De plus, avec la miniaturisation de l'électronique et les conditions d'environnement de plus en plus sévères, ces obstacles deviennent critiques et les solutions actuelles ne sont plus compatibles. Les demandes de ce marché deviennent donc de plus en plus strictes en termes de prédiction de durée de vie et de contrôle de fiabilité.L'objectif de ce projet est de comprendre et de concevoir une nouvelle formulation d'alliage sans plomb afin de développer une alternative à l'alliage plombé haute température et un alliage pour les applications haute fiabilité et en accord avec les directives gouvernementales. Des approches expérimentales avancées comme la nano-indentation, le suivi de l'évolution de la microstructure par SEM et par EDS mapping, l'étude des effets du vieillissement thermique sur la croissance de la taille des grains avec de la lumière croisée polarisée de microscopie optique etc seront utilisées pour développer un alliage sans plomb qui convienne aux exigences des applications automobile et pipeline / The urgent need for removing lead from solder alloys led to the very fast introduction of lead-free solder alloys without a deep knowledge of their behaviour. As a consequence, additional issues raised (increased thermally induced problems during soldering process, a too wide range of possible available alternative alloy formulations), while problems related to current solder alloys remained unsolved (the constant change of the solder alloy microstructure, empirical predicting lifetime methodology). All the above mentioned issues alter stability and reliability of the application specific performances of the solder alloy, and subsequently of the whole electronic module. These problems become critical and are no longer compatible, as the market goes towards miniaturization and harsh environment conditions. These market trends now require stricter life time prediction and reliability control. Objective of this project is to understand and design a novel lead-free solder formulation to develop a potential alternative to lead-based high temperature melting point solder for high reliability requirements and in accordance with governmental directives. An advanced experimental approach like nanoindentation, microstructure evolution with SEM and EDS mapping, thermal aging effects on continuous grain size growth with cross polarized light of optical microscopy etc. would be implemented to develop doped-SAC lead-free solders for the best-fit to requirements in automotives and pipelines applications

L’accroissement des besoins en énergie électrique pour les systèmes embarqués et leur augmentation de puissance nécessitent de concevoir des systèmes d’électronique de puissance toujours plus performants. Une solution d’avenir concerne la mise en œuvre de composants à base de diamant qui permettent l’augmentation conséquente des tensions et courants mis en jeux, mais aussi de la température maximale de jonction admissible. Le cadre de ces travaux est celui du projet de recherche Diamonix 2, qui concerne l’étude et l’élaboration d’un composant diamant fonctionnant à haute température. L’objectif du travail doctoral présenté ici est l’étude du packaging haute température de ce type de composant diamant. Plusieurs choix de matériaux et de techniques aptes à l’élaboration d’un assemblage de puce diamant sur un substrat métallisé ont été effectués. La caractérisation microstructurale et mécanique de trois types de jonctions ont été réalisées (refusion d’un alliage AuGe, frittage de nano pâtes d’argent et diffusion en phase solide d’indium dans des couches d’argent). Des essais mécaniques de cisaillement de divers assemblages ont permis d’évaluer le comportement thermomécanique des jonctions et des interfaces. Les essais de cisaillement ont servi à l’identification inverse des paramètres interfaciaux d’un modèle de zones cohésives, pour différents types d’interfaces. Des modèles éléments finis d’assemblage, incluant le comportement viscoplastique des jonctions et des lois d’endommagent des interfaces, ont servi à simuler le comportement thermomécanique du packaging d’un composant diamant. / The increase of electric power demand for embedded systems requires more efficient power electronics modules. A solution to reach this goal relates to the use of diamond-based components that allow high voltage, current density and the maximum allowable junction temperature. The framework is the same as that of the Diamonix 2 research project, which involves the elaboration and the study of a diamond-based die dedicated to high temperature environment. The purpose of the present work is to optimize and simulate the thermomechanical behavior of high temperature diamond die packaging. To reach this goal, the choice of materials that allow high temperature assemblies of diamond die/ceramic substrate was done (AuGe solder alloy, sintering of nano-silver paste, transient liquid phase bounding of indium in silver layers). Microstructural and mechanical characterization of the attachment and the diamond die/junction was realized. Nanoindentation and shear tests are performed for the mechanical characterization. Shear tests results carried out on the two assemblies have been used to identify the interfacial parameters of the bilinear cohesive zone model (CZM) for the diamond die/junction and ceramic substrate/junction interfaces. Finite element modelling of the diamond component packaging including viscoplastic behavior of the junctions and damage law of the interfaces of assemblies were built.

No description available.

Le développement de composants de puissance à base de carbure de silicium (SiC) permet la réalisation d’interrupteurs pouvant fonctionner au-delà de 200°C. Le silicium présente plus de limitations au niveau physique du matériau qu’au niveau des technologies d’assemblages. Le SiC est un matériau semi-conducteur grand gap ce qui permet d’obtenir des courants de fuite inverse qui restent faibles à haute température ; d’où un fort intérêt pour des applications haute température. Mise à part son utilisation à des températures pouvant dépasser les 300°C, c’est un matériau qui permet aussi d’augmenter les fréquences de commutation ainsi que la densité de puissance par rapport à des composants à technologie silicium. Ceci en fait un candidat idéal pour des applications forte puissance dans le domaine de la traction, des protections de réseaux électriques ou de la transmission et de la distribution d’énergie. L’utilisation du SiC pour une application haute température pose le problème de son packaging, des choix de matériaux et de sa configuration. Cette thèse a pour but d’effectuer une étude de fiabilité et de durée de vie des briques technologiques d’assemblage et de connexions nécessaires à la réalisation d’un cœur de puissance haute température à base de JFET SiC. Une étude des différentes technologies d’assemblages de convertisseurs de puissance haute température est effectuée afin de définir différentes briques technologiques constitutives de ces systèmes. Cette première étude nous permet de procéder à une sélection de certaines technologies d’assemblages comme le frittage de pâtes d’argent pour la technologie de report de puces. Ces briques technologiques feront l’objet d’études plus approfondies allant de la réalisation de véhicules tests jusqu’à la mise au point des essais de cyclages associés aux techniques d’analyse nécessaires à l’étude de leur défaillance.Les études expérimentales concernent des essais de cyclage passif et de stockage thermique, l’apparition de délaminages en cours de cyclage thermique (scan acoustique, RX), le report par frittage de pâtes d’argent nano et microscopiques et la caractérisation électrique et thermique (Rth, I[V]). / The development of power components based on silicon carbide (SiC) allows for the design of power converter operating at high temperature (above 200 or 300°C). SiC is a semiconductor material with a large band gap that not only can operate in temperatures exceeding 300°C but also offers fast switching speed, high voltage blocking capability and higher thermal conductivity compared to silicon technology components. The classical die attach technology uses high temperature solder alloys which melt at around 300°C. However, even a soldered die attach with such high melting point can only operate up to a much lower temperature. Alternative die attach solutions have recently been proposed: Transient Liquid Phase Bonding, soldering with higher melting point alloys such as ZnSn, or silver sintering.Silver sintering is a very interesting technology, as silver offers very good thermal conductivity (429W/m.K, better than copper), relatively inexpensive (compared to alternative solutions which often use gold), and has a very high melting point (961°C).The implementation of two silver-sintering processes is made: one based on micrometer-scale silver particles, and one on nano-meter-scale particles. Two substrate technologies are investigated: Al2O3 DBC and Si3N4 AMB. After the process optimization, tests vehicles are assembled using nano and micro silver particles paste and a more classical high-temperature die attach technology: AuGe soldering. Multiple analyses are performed, such as thermal resistance measurement, shear tests and micro-sections to follow the evolution of the joint during thermal cycling and high-temperature storage ageing.