A Tranformada Rápida de Fourier (FFT) é apresentada como um algoritmo que calcula a Transformada Discreta de Fourier mais eficientemente, do ponto de vista computacional. Uma versão mais moderna do algoritmo de Cooley e Tukey é considerada com a finalidade de se obter aplicações da FFT em algoritmos puramente algébricos, como operações de polinômios e a multiplicação de inteiros. Nas aplicações em questão, são levados em conta os aspectos computacionais e algumas implementações são apresentadas.

A Tranformada Rápida de Fourier (FFT) é apresentada como um algoritmo que calcula a Transformada Discreta de Fourier mais eficientemente, do ponto de vista computacional. Uma versão mais moderna do algoritmo de Cooley e Tukey é considerada com a finalidade de se obter aplicações da FFT em algoritmos puramente algébricos, como operações de polinômios e a multiplicação de inteiros. Nas aplicações em questão, são levados em conta os aspectos computacionais e algumas implementações são apresentadas.

A Tranformada Rápida de Fourier (FFT) é apresentada como um algoritmo que calcula a Transformada Discreta de Fourier mais eficientemente, do ponto de vista computacional. Uma versão mais moderna do algoritmo de Cooley e Tukey é considerada com a finalidade de se obter aplicações da FFT em algoritmos puramente algébricos, como operações de polinômios e a multiplicação de inteiros. Nas aplicações em questão, são levados em conta os aspectos computacionais e algumas implementações são apresentadas.

Made available in DSpace on 2014-06-12T15:52:14Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / Conselho Nacional de Desenvolvimento Científico e Tecnológico / Devido à grande demanda da comunidade científica para o aumento da precisão em cálculos científicos, com redução no tempo de processamento e na potência dissipada pelos algoritmos em sua execução, estudos têm demonstrado que dispositivos especiais, como FPGAs (Field Programmable Gate Arrays), que trabalham, em geral, como co-processadores, podem em muito ajudar nesta linha de pesquisa. Muito já foi implementado e testado, porém a limitação de se trabalhar com números inteiros, que possuem um intervalo reduzido de representação numérica, imposta pela arquitetura nativa dos FPGA, incentivaram os pesquisadores a procurarem alternativas de como aumentar a precisão na plataforma. Esta pesquisa voltou-se para o estudo e a adaptação do padrão aritmético IEEE 754, largamente utilizado em computadores comuns e DSPs, ambos com grande capacidade de representação numérica, para FPGAs. Desta forma, uma adaptação mais natural dos algoritmos já existentes, que precisam ser acelerados, seria possível com os novos recursos na nova plataforma. Esta flexibilidade oferecida pelo novo ambiente de desenvolvimento concebeu muitas alternativas de viabilidade do projeto, gerando assim, uma grande quantidade de Ip-cores (uma biblioteca de cores) que realizam a mesma tarefa, entretanto de maneiras diferentes. Este trabalho tem como objetivo principal desenvolver o algoritmo da transformada rápida de Fourier (FFT) em hardware, para FPGAs. Este software Ip-core, bastante utilizado em aplicação científicas, particularmente em processamento digital de sinais, foi desenvolvido utilizando operações aritméticas números de ponto flutuante, padrão IEEE 754, com uma boa adaptabilidade. No Ip-core desenvolvido todas as operações aritméticas complexas, que o algoritmo demanda, foram encapsuladas para futuras melhoras sejam facilmente implementadas. Isto permite que, caso algum novo core aritmético, com melhor qualidade, venha a ser desenvolvido, o mesmo poderá facilmente substituir um core existente

The P3RMA (Programmable, Parallel, and Predictable Random Memory Access) processor, currently being developed at Linköping University Sweden, is an attempt to solve the problems of parallel computing by utilizing a parallel memory subsystem and splitting the complexity of address computations with the complexity of data computations. It is targeted at embedded low power low cost computing for mobile phones, handsets and basestations among many others. By studying the radix-2 FFT using the P3RMA concept we have shown that even algorithms with a complex addressing pattern can be adapted to fully utilize a parallel datapath while only requiring additional simple addressing hardware. By supporting this algorithm with a SIMT instruction almost 100% utilization of the datapath can be achieved. A simulator framework for this processor has been proposed and implemented. This simulator has a very flexible structure featuring modular addition of new instructions and configurable hardware parameters. The simulator might be used by hardware developers and firmware developers in the future.

I detta projekt undersöker vi om man kan bygga en maskinaktivitetssensor med hjälp av en enkretsdator som genom en accelerometer mäter en maskins vibrationer. Sensorn skall generera en statussignal. Accelerometern ger en mätbar signal baserad på maskinens vibrationer. Enkretsdatorn används för att sampla, transformera och analysera signalen och generera statusinformation. Med LabView kan vi spara, studera och analysera olika signaler och olika transformer. Vi studerar maskinvibrationer i LabView och beslutar att 5 kHz sampling räcker för att fånga intressanta vibrationer. Vi jämför transformers egenskaper och beräkningskrav och väljer Fouriertransform som analysmetod. Vi beräknar att en Atmel ARM SAM7S256 kan utföra uppgiften och implementerar interruptbaserad signalsampling, frekvensanalys och en beslutsrutin som resulterar i en utsignal med statusinformation. / In this project we examine the possibility to create a machine activity sensor by a one-chip computer that measures a machines vibrations through an accelerometer. The sensor shall generate a status signal. The accelerometer is used to give a measurable signal of a machines vibrations. The one-chip computer is used to sampel, transform and analyze this signal and generate a status signal. With LabView we can save, study and analyze different signals and their different transforms. By studying machine vibrations in LabView we decide that sampling at 5 kHz is sufficient. By comparing different transformations in regards to performance and calculation needs we choose Fast Fourier Transform as analyzing tool. We calculate that a ARM SAM7S256 can manage the task and implement an interrupt based sampling, frequency analysis and decision making routine which results in a status signal.

With the advancements in technology and computing environment capabilities, the number of devices that people carry has increased exponentially. This increase initially occurred as a result of necessity to monitor the human body condition due to chronic diseases, heart problems etc. Later, individuals’ interest was drawn towards self-monitoring their physiology and health care. This is achieved by implanting various sensors that can proactively monitor the human body based on medical necessity and the health condition of the user. Sensors connected on a human body perceive phenomena such as locomotion or heartbeat, and act accordingly to form a Body Area Network. The primary concern of these sensors is to ensure a secure way of communication and coordination among the devices to form a flawless system. A secondary concern is wireless sensor authentication, which ensures trustworthiness and reliable gathering of a user’s data. To address this concern, we designed a secure approach using low cost accelerometers to authenticate sensors in Body Area Networks. To ensure authentication in on-body sensor networks, we need a mechanism which intuitively proves all the communicating nodes are trusted ones. In order to achieve sensor authentication, we used accelerometer data gathered from sensors to distinguish whether or not the devices are carried on waist of same individual’s body. Our approach is focused at analyzing walking patterns recorded from smartphone accelerometers placed in the same location of the user’s body, and we present results showing these sensors record similar pattern.

This thesis deals with designing and implementing autonomous decoder for RTTY communication. Theoretical part of the thesis deals with researching the RTTY technology and FSK modulation, which it uses, focusing mainly on the methods of demodulation. Next part of the thesis compares suitability of available platforms. Practical part of the thesis describes the design and implementation of circuit board, firmware and computer application. The device is using STM32 microcontroller. Firmware was developed in C++ using Arduino. The computer application was created by using C\# and WPF. 3 methods of FSK demodulations were implmented. One is using a FFT algorithm. Other two calculate frequency based on the period of square signal.

The theme of this thesis is presentation of the CompactRIO platform by National Instruments with its range of hardware and the possibility of using this platform for the frequency measurement of analog signals. The result of this thesis is software equipment for this device focusing on the frequency measurement of analog signals and experimental verification of posibilities of a specific configuration of this platform in the range of measurable frequencies.

The production of faulty parts poses significant challenges for production facilities, as it leads to increased inventory levels, operating costs, and impedes overall productivity. Despite its fundamental nature, this issue remains prevalent in manufacturing operations. To effectively reduce the rate of faulty parts, it is crucial to have a thorough understanding of the manufacturing process and exercise control by monitoring various parameters.  The aim of this study is to investigate the right prerequisites which enable quality assurance through in-line failure detection by vibration analysis. The research questions formulated for this thesis are as follows:  RQ1: What are the essential prerequisites for quality assurance through in-line failure detection by vibration analysis in the machining of splines? RQ2: How suitable is the use of vibration measurements in identifying and sorting out poor quality in the specific machining process of splines? The study was conducted through a literature review and a single case study of a gear hobbing process in an industrial manufacturing company.  The collection of data was acquired via interviews, observations, and vibration measurements during the spline manufacturing process. To analyse the collected data several tools got used. Python was used as the tool for performing several operations on the dataset, such as FFT of the vibration signals. To later visualize the results which facilitated the analysis of the entire dataset.  The results of the study indicate several similarities between the documented fault progression in gear systems and the manufacturing of splines. However, further research is needed to identify the core differences between these two fault progressions.  Furthermore, the study identified the essential prerequisites for implementing vibration analysis as an in-line failure detection method in spline manufacturing operations. Additionally, it concluded on the suitability of vibration analysis for identifying faults in this context.