High-temperature integrated circuit (IC) design is one of the new frontiers in microelectronics that can significantly improve the performance of the electrical systems in extreme environment applications, including automotive, aerospace, well-logging, geothermal, and nuclear. Power modules (DC-DC converters, inverters, etc.) are key components in these electrical systems. Power-to-volume and power-to-weight ratios of these modules can be significantly improved by employing silicon carbide (SiC) based power switches which are capable of operating at much higher temperature than silicon (Si) and gallium arsenide (GaAs) based conventional devices. For successful realization of such high-temperature power electronic circuits, associated control electronics also need to perform at high temperature. In any power converter, gate driver circuit performs as the interface between a low-power microcontroller and the semiconductor power switches. This dissertation presents design, implementation, and measurement results of a silicon-on-insulator (SOI) based high-temperature (>200 _C) and high-voltage (>30 V) universal gate driver integrated circuit with high drive current (>3 A) for SiC power switches. This mixed signal IC has primarily been designed for automotive applications where the under-hood temperature can reach 200 _C. Prototype driver circuits have been designed and implemented in a Bipolar-CMOS- DMOS (BCD) on SOI process and have been successfully tested up to 200 _C ambient temperature driving SiC switches (MOSFET and JFET) without any heat sink and thermal management. This circuit can generate 30V peak-to-peak gate drive signal and can source and sink 3A peak drive current. Temperature compensating and temperature independent design techniques are employed to design the critical functional units like dead-time controller and level shifters in the driver circuit. Chip-level layout techniques are employed to enhance the reliability of the circuit at high temperature. High-temperature test boards have been developed to test the prototype ICs. An ultra low power on-chip temperature sensor circuit has also been designed and integrated into the gate-driver die to safeguard the driver circuit against excessive die temperature (_ 220 _C). This new temperature monitoring approach utilizes a reverse biased p-n junction diode as the temperature sensing element. Power consumption of this sensor circuit is less than 10 uW at 200 _C.

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

Organisations tend to focus more and more on product and process development to increase their competitiveness. Several major organisations, among them ABB, have developed models aimed to more effectively control and manage product development processes. ABB is using its standardised model ABB Gate Model for this. The purpose of this thesis is to analyze how the introduction of ABB Gate Model has affected the outcome of decisions and also the decision-making in the product development process. The study is limited to elucidate the version of ABB Gate Model handling product development projects. No deeper study is conducted regarding the information used or the criteria for the gate decisions; instead, the focus is to findelements in basis for the decision- making that have a greater significance for the outcome at some gate or at specific types of gate decisions. The empirical data of the thesis has to a great extent been collected through interviews with respondents from both of the studied units and also the unit in charge of the implementation and development of ABB Gate Model. The study shows that ABB Gate Model does not to any significant extent affect the outcome of the decisions in the product development projects. In general, the same decisions are made as before and projects are seldom cancelled. The foremost effects of ABB Gate Model at the units are: increased clarity and support to the operational work, improved co- ordination between the units functional departments, and contributed to make essential aspects of the product development projects visible and taken into consideration.

In this thesis, various issues regarding normally-ON silicon carbide (SiC)Junction Field-Effect Transistors (JFETs) are treated. Silicon carbide powersemiconductor devices are able to operate at higher switching frequencies,higher efficiencies, and higher temperatures compared to silicon counterparts.From a system perspective, these three advantages of silicon carbide can determinethe three possible design directions: high efficiency, high switchingfrequency, and high temperature.The structure designs of the commercially-available SiC power transistorsalong with a variety of macroscopic characteristics are presented. Apart fromthe common design and performance problems, each of these devices suffersfrom different issues and challenges which must be dealt with in order to pavethe way for mass production. Moreover, the expected characteristics of thefuture silicon carbide devices are briefly discussed. The presented investigationreveals that, from the system point-of-view, the normally-ON JFET isone of the most challenging silicon carbide devices. There are basically twoJFET designs which were proposed during the last years and they are bothconsidered.The state-of-the-art gate driver for normally-ON SiC JFETs, which wasproposed a few years ago is briefly described. Using this gate driver, theswitching performance of both Junction Field-Effect Transistor designs wasexperimentally investigated.Considering the current development state of the available normally-ONSiC JFETs, the only way to reach higher current rating is to parallel-connecteither single-chip discrete devices or to build multichip modules. Four deviceparameters as well as the stray inductances of the circuit layout might affectthe feasibility of parallel connection. The static and dynamic performance ofvarious combinations of parallel-connected normally-ON JFETs were experimentallyinvestigated using two different gate-driver configurations.A self-powered gate driver for normally-ON SiC JFETs, which is basicallya circuit solution to the “normally-ON problem” is also shown. This gatedriver is both able to turn OFF the shoot-through current during the startupprocess, while it also supplies the steady-state power to the gate-drivecircuit. From experiments, it has been shown that in a half-bridge converterconsisting of normally-ON SiC JFETs, the shoot-through current is turnedOFF within approximately 20 μs.Last but not least, the potential benefits of employing normally-ON SiCJFETs in future power electronics applications is also presented. In particular,it has been shown that using normally-ON JFETs efficiencies equal 99.8% and99.6% might be achieved for a 350 MW modular multilevel converter and a40 kVA three-phase two-level voltage source converter, respectively.Conclusions and suggestions for future work are given in the last chapterof this thesis. / I denna avhandling behandlas olika aspekter av normally–ON junction–field–effect–transistorer (JFETar) baserade på kiselkarbid (SiC). Effekthalvledarkomponenteri SiC kan arbeta vid högre switchfrekvens, högre verkningsgradoch högre temperatur än motsvarigheterna i kisel. Ur ett systemperspektivkan de tre nämnda fördelarna användas i omvandlarkonstruktionen för attuppnå antingen hög verkningsgrad, hög switchfrekvens eller hög temperaturtålighet.Såväl halvledarstrukturen som de makroskopiska egenskaperna för kommersiellttillgängliga SiC–transistorer presenteras. Bortsett från de vanligakonstruktions–och prestandaproblemen lider de olika komponenterna av ettantal tillkortakommanden som måste övervinnas för att bana väg för massproduktion.Även framtida SiC–komponenter diskuteras.Ur ett systemperspektiv är normally-ON JFETen en av de mest utmanandeSiC-komponenterna. De två varianter av denna komponent som varittillgängliga de senaste åren har båda avhandlats.State–of–the–art–drivdonet för normally-ON JFETar som presenteradesför några år sedan beskrivs i korthet. Med detta drivdon undersöks switchegenskapernaför båda JFET-typerna experimentellt.Vid beaktande av det aktuella utvecklingsstadiet av de tillgängliga normally–ON JFETarna i SiC, är det möjligt att uppnå höga märkströmmar endastom ett antal single–chip–komponenter parallellkopplas eller om multichipmodulerbyggs. Fyra komponentparametrar samt strö-induktanser för kretsenkan förutses påverka parallellkopplingen. De statiska och dynamiska egenskapernaför olika kombinationer av parallellkopplade normally-ON JFETarundersöks experimentellt med två olika gate–drivdonskonfigurationer.Ett självdrivande gate-drivdon för normally-ON JFETar presenteras också.Drivdonet är en kretslösning till “normally–ON–problemet”. Detta gatedrivdonkan både stänga av kortslutningsströmmen vid uppstart och tillhandahållaströmförsörjning vid normal drift. Med hjälp av en halvbrygga medkiselkarbidbaserade normally–ON JFETar har det visats att kortslutningsströmmenkan stängas av inom cirka 20 μs.Sist, men inte minst, presenteras de potentiella fördelarna med användningenav SiC-baserade normally-ON JFETar i framtida effektelektroniskatillämpningar. Speciellt visas att verkningsgrader av 99.8% respektive 99.5%kan uppnås i fallet av en 350 MW modular multilevel converter och i en40 kVA tvånivåväxelriktare. Sista kaplitet beskriver slutsatser och föreslagetframtida arbete. / <p>QC 20130527</p>

As Field-Programmable Gate Array (FPGA) capacity can now support several processors on a single device, the scalability of FPGA design tools and methods has emerged as a major obstacle for the wider use of FPGAs. For example, logic synthesis, which has traditionally been the fastest step in the FPGA Computer-Aided Design (CAD) flow, now takes several hours to complete in a typical FPGA compile. In this work, we address this problem by focusing on two areas. First, we revisit FPGA logic synthesis and attempt to improve its scalability. Specifically, we look at a binary decision diagram (BDD) based logic synthesis flow, referred to as FBDD, where we improve its runtime by several fold with a marginal impact to the resulting circuit area. We do so by speeding up the classical cut generation problem by an order-of-magnitude which enables its application directly at the logic synthesis level. Following this, we introduce a guided partitioning technique using a fast global budgeting formulation, which enables us to optimize individual “pockets” within the circuit without degrading the overall circuit performance. By using partitioning we can significantly reduce the solution space of the logic synthesis problem and, furthermore, open up the possibility of parallelizing the logic synthesis step. The second area we look at is the area of Engineering Change Orders (ECOs). ECOs are incremental modifications to a design late in the design flow. This is beneficial since it is minimally disruptive to the existing circuit which preserves much of the engineering effort invested previously in the design. In a design flow where most of the steps are fully automated, ECOs still remain largely a manual process. This can often tie up a designer for weeks leading to missed project deadlines which is very detrimental to products whose life-cycle can span only a few months. As a solution to this, we show how we can leverage existing logic synthesis techniques to automatically modify a circuit in a minimally disruptive manner. This can significantly reduce the turn-around time when applying ECOs.

The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

En raison des forts gradients de dose générés par les interactions des particules avec la matière, les traitements par hadronthérapie nécessitent un contrôle très précis de la dose délivrée au patient. Les codes Monte Carlo représentent des outils indispensables dans la validation des systèmes de planification de traitement utilisé en clinique. Nous nous intéressons dans cette thèse au calcul de la dose physique à l'aide des simulations Monte Carlo Geant4/Gate. Nous étudions l'ajustement de plusieurs paramètres qui peuvent influencer la précision du calcul de dose requise en clinique (2%, 2mm) pour un faisceau d'ions carbone de 300 MeV/u dans l'eau. Ces paramètres sont : le seuil de production des particules secondaires et la taille maximale d'un segment de la trace de particule. Les critères de tolérance sur la valeur et la localisation de la dose sont fixés de manière à avoir le meilleur compromis en termes de distribution spatiale et de temps de calcul. Nous proposons ici des paramètres permettant d'atteindre ces critères de précision. Dans la deuxième partie du travail, nous étudions la réponse des films radiochromiques MDv2-55 pour le contrôle qualité des faisceaux d'ions carbone et protons. Nous avons en particulier observé et étudié l'effet de saturation de ces films dosimétriques pour les irradiations à TEL élevés (≥ 20 KeV/µm) dans des milieux homogènes et hétérogènes. Cet effet est dû à la forte densité d'ionisation autour de la trace de particule. Nous avons proposé et développé un modèle appelé " RADIS RAdiochromic films Dosimetry for Ions using Simulations " qui permet de prédire la réponse de ces films avec la prise en compte de cet effet de saturation. Ce modèle est basé sur la réponse des films en photons et la saturation des films à des dépôts d'énergies linéïques élevés calculée par Monte Carlo. Plusieurs types de faisceaux ont été étudiés : ions carbone, protons et photons à différentes énergies. Ces expérimentations ont été menées au Grand Accélérateur National d'Ions Lourds (GANIL), au Centre de protonthérapie d'Orsay (CPO), au Centre A. Lacassagne (CAL) et au Centre Léon Bérard (CLB). A l'aide du modèle, nous pouvons ainsi reproduire la densité optique des films le long du profil de Bragg pour tous les faisceaux avec une précision meilleure que 2%.

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

Soft computing techniques are generally well-suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environment. To demonstrate their applicability, two intelligent controllers based upon fuzzy logic theories and neural network paradigms are designed for performing a wall-following task and an autonomous parking task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a Field Programmable Gate Array (FPGA). As the number of comparative studies of these two embedded controllers designed for the same application is limited in the literature, one of the main goals of this research work has been to evaluate and compare the two controllers in terms of hardware resource requirements, operational speeds and trajectory tracking errors in following different pre-defined trajectories. The main advantages and disadvantages of each of the controllers are presented and discussed in details. Challenging issues for implementation of the controllers on the FPGA platform are also highlighted. As the two controllers exhibit benefits and drawbacks under different circumstances, this research suggests as well a hybrid controller scheme as an attempt to integrate the benefits of both control units. To evaluate its performance, the hybrid controller is tested on the same pre-defined trajectories and the corresponding results are compared to that of the fuzzy logic and the neural network based controllers. For further demonstration of the capabilities of the wall-following controllers in other applications, the fuzzy logic and the neural network controllers are used in a parallel parking system. We see this work to be a stepping stone for further research work aiming at real world implementation of the controllers on Application Specified Integrated Circuit (ASIC) type of environment.