ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / Today’s data acquisition systems are typically comprised of data collectors connected to multiplexers via serial, point-to-point links. Data flows upstream from the sensors or avionics buses to the data acquisition units, to the multiplexer and finally to the recorder or telemetry transmitter. In a networked data acquisition system, data is transported through the network “cloud”. At the core of the network “cloud” is the network switch. The switch is responsible for distributing and directing data within the network. Network switches are commonplace in the commercial realm. Many businesses today could not function without them. A network-based data acquisition system, however, places additional burdens on the network switch. As in a commercial network, the switch in a data acquisition system must be able to distribute data packets within the network. In addition, it must be able to perform in a harsh environment, occupy a minimal amount of space, operate with limited or no external cooling, be configurable, and deal with the distribution of time information. This paper describes the required features of a ruggedized network switch and the implementation challenges facing its design. As a core component of a network-based data acquisition system, an ideal switch must be capable of operating in a large number of configurations, transporting and aggregating data between data sources and data sinks, with a mixture of devices operating at rates ranging from a few thousand bits per second to several gigabits per second, over twisted pair or fiber optic links. To ensure time coherency, the switch must also facilitate a time distribution mechanism, e.g., IEEE-1588 Precision Time Protocol (PTP). The gigabit switch described here uses the PTP to implement an end-to-end clock synchronization, for distributed acquisition nodes, to within 300 nanoseconds.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Gigabits and hundreds of megabit communication buses are starting to appear as the avionic buses of choice for new or upgraded airborne systems. This trend presents new challenges for instrumentation engineers in the areas of high speed data multiplexing, data recording, and data transmission of flight safety information. This paper describes the approach currently under development to acquire data from several types of high-speed avionic buses using distributed multiplexer and acquisition units. Additional input data may include PCM, wideband analog data, discrete, real-time video and others. The system is capable of multiplexing and recording all incoming data channels, while at the same time providing data selection down to the parameter level from input channels for transmission of flight safety information. Additionally, an extensive set of data capture trigger/filter/truncation mechanisms are supported.

<p>Here at ISY research is performed on network processors. In order to evaluate the processors there is a need to have full control of every aspect of the transmission. This is not the case if you use a proprietary technology. Therefore the need for a well documented gigabit Ethernet network interface has emerged. </p><p>The purpose of this thesis work has been to design and implement an open source gigabit Ethernet controller in a FPGA together with a device driver for the Linux operating system Implementation has been done in Verilog for the hardware part and the software was developed in C.</p><p>We have implemented a fully functional gigabit Ethernet interface onto a Xilinx Virtex II-1500 FPGA together with a Linux device driver. The design uses approximately 7200 LUTs and 48 block RAMs including the opencores PCI bridge.</p>

Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: Fouad Kiamilev, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: Fouad Kiamilev, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

At Saab Dynamics AB there are a number of projects where cameras are an important part of a sensor system. Examples of such projects are monitoring for civil security and 3D mapping, where several cameras are used. The cameras can for example be located in airplanes, helicopters or cars and therefore it is important to have a robust function for recording data. One way to achieve a quick recording with sufficient storage size is to use SATA flash disks. To reduce the size and power consumption of the recording equipment and to enable project-specific adaptations it is desirable to use an FPGA as an interface to SATA devices. This thesis concerns the development of such an interface implemented on an FPGA. The theory behind the SATA interconnect standard is described along with the design work and its challenges.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Laskar, Joy; Committee Member: Cressler, John; Committee Member: Tentzeris, Manos. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved. / text

10 Gigabit Ethernet (GbE) demands faster optical sources to support high modulation rates. At the same time, the allowable margin in the 10 GbE link power budget is decreasing. This means that a 10 GbE system is unable to support as many tight bends, and it is more difficult to avoid the costly downtime that results when the allowable margin is exceeded. The recent introduction of bend-optimized (BO) multimode fiber (MMF) provides a clear solution. 850 nm vertical cavity surface emitting lasers (VCSELs) and MMFs have long been the most cost effective choice for short reach premise applications. As will be shown, the combination of BO-MMF with VCSELs is even more attractive.Historically, MMF systems operating at low bit rates of 10-100 Mbps used light-emitting diodes (LED) sources, which launch nearly equal power into every fibermode. This launch is approximated by the overfilled launch (OFL), which is still used to characterize the core diameter and numerical aperture of MMF. Unlike LEDs, VCSELs typically underfill the fiber core and are better represented by an encircled flux launch (EFL). Using OFL to evaluate a VCSEL-based MMF system could therefore produce inaccurate and misleading results. A recent study [1] characterized the macrobend loss of MMF with overfilled and restricted mode offset launch conditions. In this study, the MMFs performance with an EFL is evaluated, which is a more relevant launch condition for laser transmission. The impact of both launch conditions, OFL and EFL, on MMF performance is studied and compared.We characterize macrobend losses at small bend radii and their impact on thebandwidth for both standard 50/125 um MMF and a newly introduced BO-MMF.In addition, the 10 GbE link performance is also evaluated using the IEEE link model P802.3ae3.The simulation results illustrate that both macrobend loss and bandwidth are vital to the overall optical link performance. The 10 GbE link performance of the standard fiber deteriorates with macrobends, while the bend-optimized fiber is insensitive to the deployment conditions.

Here at ISY research is performed on network processors. In order to evaluate the processors there is a need to have full control of every aspect of the transmission. This is not the case if you use a proprietary technology. Therefore the need for a well documented gigabit Ethernet network interface has emerged. The purpose of this thesis work has been to design and implement an open source gigabit Ethernet controller in a FPGA together with a device driver for the Linux operating system Implementation has been done in Verilog for the hardware part and the software was developed in C. We have implemented a fully functional gigabit Ethernet interface onto a Xilinx Virtex II-1500 FPGA together with a Linux device driver. The design uses approximately 7200 LUTs and 48 block RAMs including the opencores PCI bridge.