The main goal of this research is to develop a new type of antenna, called reconfigurable antenna, which can replace multiple antennas required to enhance the effectiveness of a robust communication system. A recongurable antenna integrated with switching elements can dynamically change its properties, namely, frequency of operation, radiation pattern (the three-dimensional coverage of antenna), and polarization (the electrical orientation of the antenna). Depending on the requirement, a single antenna can function as multiple an- tennas, therefore, the name Multi-functional Recongurable Antenna (MRA). United States (US) Public Safety (PS) responders (police, re-ghters, emergency medical services, etc.) can effectively respond to human-made or natural catastrophies if they are equipped with robust communication systems supported by MRA. Wireless implementations of computer accessories (wireless HDMI, wireless storage to external hard-drive, etc.) that require high speed data communication are supported by 60 GHz communications. Equipping these devices with MRA could further increase the speed of communication, thereby resulting in a robust communication. In this work, pin-diodes and Micro Electro Mechanical Switches (MEMS) are integrated on the MRAs to reconfigure (dynamically change) its properties namely frequency and radiation pattern. An MRA capable of operating over 220, 470, 800, 4900 MHz PS bands is designed, manufactured, tested, and characterized. Another MRA capable of changing its radiation pattern over 4.94-4.99 GHz band is designed, manufactured, tested, and characterized. The design of radiation pattern recongurable MRA and Multi-functional Reconfigurable Antenna Array (MRAA) for 60 GHz communication is also accomplished. The MRAA is designed in order to enhance the MRA's capability to receive or transmit more power.

In recent years, multi-core processors and multi-processor networks have grown in popularity as a solution to the limits on increasing clock speed, rising power consumption, and the nanometer manufacturing processes. Multi-core processors and multi-processor networks are seen as the next step in the advancement of computational capabilities by way of concurrent processing. However, parallel software design is difficult due to the immaturity of scalable architectures and software development environments for multi-core hardware. How should processors effectively and quickly pass information, with as little overhead as possible? What kind of communication architecture is best suited for parallelism? How can large-scale architectures be quickly produced, verified and properly utilized by software? Using commercially available FPGA development boards, Xilinx tools and components, this thesis offers a light-weight solution to these questions for effective, low-overhead, low-latency multi-core communication and fast prototyping of multi-processor networks for scalable processor arrays. / Master of Science

Neste trabalho propomos e analisamos algoritmos de alocação dinâmica de banda para rede óptica passiva (PON) de acesso padrão GPON (Gigabit PON). Estes algoritmos utilizam dados oriundos de SLA (service level agreement) para gerenciar a alocação de banda e classificar em 4 contêineres de tráfego (T-CONT) o tráfego gerado em 16 ONUs (optical network unit). Na transmissão upstream é utilizada a técnica de multiplexação por divisão de tempo (TDM) para gerenciar o acesso ao meio, evitando colisões. O primeiro algoritmo proposto aloca banda garantida para as ONUs e distribui a banda não utilizada de acordo com critério baseado em três SLAs. A taxa de bit upstream é 1,25 Gbps e o desempenho do algoritmo é analisado com base na variação do atraso de pacotes em função do tráfego gerado nas ONUs. O segundo algoritmo proposto utiliza ponderação de tráfego. Neste, analisamos o comportamento dos atrasos e a quantidade de banda solicitada e atendida por ONU quando as bandas garantida e extra são alteradas. Por fim, acrescentamos em nossa implementação um intervalo para o processamento do algoritmo de alocação dinâmica de banda (DBA) e resposta do hardware relacionado ao ciclo de interrogação. Então, analisamos o atraso de pacotes quando variamos o intervalo de processamento do DBA. Ao final, propomos uma solução preliminar para minimizar estes atrasos. Os resultados obtidos por meio de simulação computacional mostram a versatilidade dos algoritmos. / In this work we propose and analyze the performance of dynamic bandwidth allocation algorithms for optical passive networks (PON) in GPON standard (Gigabit PON). These algorithms use data from SLA (service level agreement) to manage bandwidth allocation and classify in 4 traffic containers (T-CONT) the traffic generated by 16 ONUs (optical network unit). In the upstream transmission the time division multiplexing (TDM) technique is used to manage the medium access, avoiding collisions. The first proposed algorithm allocates guaranteed bandwidth for the ONUs and distributes the bandwidth not used according to the criteria based on three SLAs. The upstream bit rate is 1.25 Gbps and the algorithm performance is analyzed based on the packets delay variation versus the traffic generated by ONUs. The second proposed algorithm uses weighted traffic. In this, we analyze the delay performance and the required bandwidth for each ONU and how much it is served when the guaranteed and extra bandwidth are changed. Finally, we added in our implementation an interval for the processing of the dynamic bandwidth allocation algorithm (DBA) and response of the hardware related to the interrogation cycle. In the end, we propose a preliminary solution to minimize these delays. The results obtained by means of computational simulation show the versatility of the algorithms.

[pt] O principal objetivo desta dissertação consiste na geração de novas funcionalidades inteligentes em redes ópticas associadas aos protocolos IP e Gigabit Ethernet, através da utilização de circuitos integrados programáveis operando na taxa do Gigabit. A padronização Ethernet é apresentada através das camadas PHY e MAC, destacando suas funções, interfaces e os tipos de chips disponíveis no mercado. A camada PHY do padrão Ethernet para meios ópticos é detalhada. Algumas tecnologias de chips são discutidas, entre elas o crescimento dedicado, os ASICs, as NPUs e as tecnologias programáveis: FPGAs e CPLDs. O conceito de inteligência óptica e o perfil de camadas equivalentes associados a este conceito são introduzidos. Um novo elemento de rede dedicado à inserção de sinalização na camada óptica é apresentado, destacando-se sua estrutura, sua realização, seu detalhamento para utilização em redes. Diversas montagens experimentais com o elemento desenvolvido são utilizadas para demonstrar as características do sistema, entre elas a eficiência da utilização da tecnologia de FPGAs e a transparência da inteligência na camada óptica para o padrão Ethernet. / [en] The main objective of this work is the generation of new functionalities in optical networks, associated to the Ethernet and IP protocols, by the use of programmable integrated circuits operating in Gigabit rates. The Ethernet standard is presented through its PHY and MAC layers, highlighting its functions, interfaces and the types of commercially available ICs. The Ethernet standard PHY layer for optical media is described. Some IC technologies are discussed, such as dedicated growth, ASICs, NPUs and the programmable technologies: FPGAs e CPLDs. The concept of built-in optical intelligence and a new layers model associated to it are presented. A new network element, dedicated to the insertion of signaling in the optical layer is also presented, and special attention is dedicated to its structure, to its implementation and to the aspects of its use in networks. Several experimental setups using the developed element are shown, demonstrating the characteristics of the system, particularly the efficiency obtained by the use of FPGA technology and the transparency of the optical intelligence with respect to the Ethernet standard.

Neste trabalho propomos e analisamos algoritmos de alocação dinâmica de banda para rede óptica passiva (PON) de acesso padrão GPON (Gigabit PON). Estes algoritmos utilizam dados oriundos de SLA (service level agreement) para gerenciar a alocação de banda e classificar em 4 contêineres de tráfego (T-CONT) o tráfego gerado em 16 ONUs (optical network unit). Na transmissão upstream é utilizada a técnica de multiplexação por divisão de tempo (TDM) para gerenciar o acesso ao meio, evitando colisões. O primeiro algoritmo proposto aloca banda garantida para as ONUs e distribui a banda não utilizada de acordo com critério baseado em três SLAs. A taxa de bit upstream é 1,25 Gbps e o desempenho do algoritmo é analisado com base na variação do atraso de pacotes em função do tráfego gerado nas ONUs. O segundo algoritmo proposto utiliza ponderação de tráfego. Neste, analisamos o comportamento dos atrasos e a quantidade de banda solicitada e atendida por ONU quando as bandas garantida e extra são alteradas. Por fim, acrescentamos em nossa implementação um intervalo para o processamento do algoritmo de alocação dinâmica de banda (DBA) e resposta do hardware relacionado ao ciclo de interrogação. Então, analisamos o atraso de pacotes quando variamos o intervalo de processamento do DBA. Ao final, propomos uma solução preliminar para minimizar estes atrasos. Os resultados obtidos por meio de simulação computacional mostram a versatilidade dos algoritmos. / In this work we propose and analyze the performance of dynamic bandwidth allocation algorithms for optical passive networks (PON) in GPON standard (Gigabit PON). These algorithms use data from SLA (service level agreement) to manage bandwidth allocation and classify in 4 traffic containers (T-CONT) the traffic generated by 16 ONUs (optical network unit). In the upstream transmission the time division multiplexing (TDM) technique is used to manage the medium access, avoiding collisions. The first proposed algorithm allocates guaranteed bandwidth for the ONUs and distributes the bandwidth not used according to the criteria based on three SLAs. The upstream bit rate is 1.25 Gbps and the algorithm performance is analyzed based on the packets delay variation versus the traffic generated by ONUs. The second proposed algorithm uses weighted traffic. In this, we analyze the delay performance and the required bandwidth for each ONU and how much it is served when the guaranteed and extra bandwidth are changed. Finally, we added in our implementation an interval for the processing of the dynamic bandwidth allocation algorithm (DBA) and response of the hardware related to the interrogation cycle. In the end, we propose a preliminary solution to minimize these delays. The results obtained by means of computational simulation show the versatility of the algorithms.

[pt] O principal objetivo desta dissertação consiste na proposta de implementação de uma rede de telecomunicações utilizando novas tecnologias, enfatizando as aplicações de entretenimento. As soluções adotadas foram orientadas pelas características econômicas verificadas nas áreas nobres das regiões metropolitanas brasileiras e também pelas novas tecnologias de roteamento, chaveamento, armazenamento e distribuição local. A avaliação do custo de investimento e operacional da rede, bem como a formulação de um modelo de negócios associado a uma estrutura de serviços oferecidos foram apresentadas e desenvolvidas. A construção de um plano de negócio hipotético para avaliar a relação custo-benefício resultante da utilização da infra-estrutura da rede proposta associado ao modelo e estrutura dos serviços elaborados foi implementado e executado. Quatro alternativas de implementação de rede foram avaliadas. / [en] The present dissertation is aiming at proposing a telecommunications network implementation using some new technologies where the emphasis is put on entertainment applications. The adopted solutions try to offer a selection grid that qualitatively cope with the economic level of some selected noble metropolitan areas in Brazil and rely in new routing, switching storage and local distribution technologies. The investment evaluation, the operational network costs and the formulation of a business model associated with the respective used service structure is subsequently introduced and described. Next, a hypothetic business plan service model is launched in order to evaluate the cost-benefit ratio between the network infrastructure proposed working together with its new service model and its new structure. Four possible alternatives of network implementation were evaluated and commented.

This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.

This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.

Für die Implementierung von Hochgeschwindigkeits-LANs bieten sich gegenwärtig zwei Technologien an. Dies ist zunächst der verbindungsorientiert arbeitende Asynchronus Transfer Mode (ATM), welcher u.a. garantierte Bandbreiten ermöglicht und auch für WAN-Anwendungen einsetzbar ist. Ein Nachteil von ATM ist die Inkompatiblität zu den verbreitetsten LAN- Technologien, Ethernet und Token Ring. Für die Kopplung mit solchen LANs müssen spezielle Server herangezogen werden. Im Gegensatz dazu steht Gigabit Ethernet (GE) als Weiterentwicklung des Ethernet-Standards (IEEE 802.3). GE arbeitet verbindungslos und ist kompatibel zur Ethernet-Familie und anderen IEEE 802 konformen Technologien. Mit der Verfügbarkeit der IEEE-Standards 802.1p, 802.1x, 802.1Q und 802.1D sowie proprietären Mechanismen können mit Gigabit Ethernet LANs aufgebaut werden, die ATM-ähnliche Eigenschaften besitzen. Durch den Einsatz des TCP/IP Protokolls, welches traditionell in Netzen zur wissenschaftlichen Datenverarbeitung Verwendung findet, bleiben Eigenschaften, vor allem von ATM, verborgen. Dies betrifft insbesondere die dynamische Anforderung von Bandbreitengarantien (QoS).

Classical Molecular Dynamics simulation (MD) models the interactions of thousands to millions of particles through the iterative application of basic Physics. MD is one of the core methods in High Performance Computing (HPC). While MD is critical to many high-profile applications, e.g. drug discovery and design, it suffers from the strong scaling problem, that is, while large computer systems can efficiently model large ensembles of particles, it is extremely challenging for {\it any} computer system to increase the timescale, even for small ensembles. This strong scaling problem can be mitigated with low-latency, direct communication. Of all Commercial Off the Shelf (COTS) Integrated Circuits (ICs), Field Programmable Gate Arrays (FPGAs) are the computational component uniquely applicable here: they have unmatched parallel communication capability both within the chip and externally to couple clusters of FPGAs. This thesis focuses on the acceleration of the long range (LR) force, the part of MD most difficult to scale, by using FPGAs. This thesis first optimizes LR acceleration on a single-FPGA to eliminate the amount of on-chip communication required to complete a single LR computation iteration while maintaining as much parallelism as possible. This is achieved by designing around application specific memory architectures. Doing so introduces data movement issues overcome by pipelined, toroidal-shift multiplexing (MUXing) and pipelined staggering of memory access subsets. This design is then evaluated comprehensively and comparatively, deriving equations for performance and resource consumption and drawing metrics from previously developed LR hardware designs. Using this single-FPGA LR architecture as a base, FPGA network strategies to compute the LR portion of larger sized MD problems are then theorized and analyzed.