Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos equipamentos comerciais atuais através de duas técnicas: CES - Circuit Emulation Service e TDM nativo não estruturado. Em seguida, é introduzido o conceito de comutação digital visando sua aplicação no transporte TDM nativo estruturado em redes GPON. Nesta etapa, é proposta uma solução para este transporte, é descrito o protocolo utilizado bem como seu funcionamento. Por fim, como prova de conceito, é apresentada uma implementação em HDL (Hardware Description Language) para FPGA (Field Programmable Gate Array). / In this work we analyze and propose the use of native channeled /structured TDM (Time Division Multiplexing) in GPON (Gigabit Passive Optical Network), with emphasis on the structure for transmission of the telephone network legacy. The main target is to achieve an increase in transmitted bandwidth efficiency by fragmenting E1 signals, thus avoiding the use of circuit emulation techniques (which reduce the bandwidth efficiency due to overhead addition). Initially, it is described in TDM transport in GPON networks, as it is performed in present commercial equipment by two techniques: CES - Circuit Emulation Service and Native TDM - unstructured. Next, we introduce the concepts of digital switching aiming its application on the transport of native and structured TDM in GPON. At this stage, we propose a transport solution, describe its protocol and functionalities. Finally, for concept proof, we present an implementation in HDL (Hardware Description Language) meant to FPGA (Field Programmable Gate Array) application.

Graphics Processing Units (GPUs) are emerging as the most popular accelerator for many applications, powering the core of Machine Learning applications and many computing-intensive workloads. GPUs have typically been consideredas accelerators, with Central Processing Units (CPUs) in charge of the mainapplication logic, data movement, and network connectivity. In these architectures,input and output data of network-based GPU-accelerated application typically traverse the CPU, and the Operating System network stack multiple times, getting copied across the system main memory. These increase application latency and require expensive CPU cycles, reducing the power efficiency of systems, and increasing the overall response times. These inefficiencies become of higher importance in latency-bounded deployments, or with high throughput, where copy times could easily inflate the response time of modern GPUs. The main contribution of this dissertation is towards a GPU-centric network architecture, allowing GPUs to initiate network transfers without the intervention of CPUs. We focus on commodity hardware, using NVIDIA GPUs and Remote Direct Memory Access over Converged Ethernet (RoCE) to realize this architecture, removing the need of highly homogeneous clusters and ad-hoc designed network architecture, as it is required by many other similar approaches. By porting some rdma-core posting routines to GPU runtime, we can saturate a 100-Gbps link without any CPU cycle, reducing the overall system response time, while increasing the power efficiency and improving the application throughput.The second contribution concerns the analysis of Clockwork, a State-of-The-Art inference serving system, showing the limitations imposed by controller-centric, CPU-mediated architectures. We then propose an alternative architecture to this system based on an RDMA transport, and we study some performance gains that such a system would introduce. An integral component of an inference system is to account and track user flows,and distribute them across multiple worker nodes. Our third contribution aims to understand the challenges of Connection Tracking applications running at 100Gbps, in the context of a Stateful Load Balancer running on commodity hardware. / <p>QC 20240315</p>

This thesis is a pre-study for the design of a fiber optic transceiver system capable of transmitting Universal Serial Bus (USB) 3.2 and 2.0 signals over an optic medium. The added benefit of such a system is that transmission can potentially be achieved over longer distances than what is allowed by the Universal Serial Bus standards. Beneficial scenarios are industrial applications, media production applications or in electromagnetically noisy environments. Currently there exists transceiver systems capable of transmitting Universal Serial Bus 2.0 and the slowest of Universal Serial Bus 3.2 operating modes, but not the higher speed Universal Serial Bus 3.2 modes. The transmission of these higher speed modes with retained capability of transmitting the slower modes is the subject of investigation for this thesis. This project was kept at a theoretical level and takes into account electronics, fiber optics, data structures, networking and system design. General considerations and challenges with designing a transceiver system in question are put forward. Challenges such as the half-duplex to full-duplex conversion necessary for transceiving Universal Serial Bus 2.0 over fiber, propagation delay, single ended zeroes and low speed signaling carried out by Universal Serial Bus 3.2. Then, two architectures for fiber transceivers and their basic respective structures are proposed: parallel and serial. They are then discussed with regards to their challenges, strengths and weaknesses. It is concluded that since there are no technological limitations, both architectures are plausible to implement. The parallel architecture being the easier to implement because it features a more complex optical module. Therefore reducing the complexity of the interfacing and packeting to the optical module when compared to the serial architecture. / Detta examensarbete är en förstudie för design utav ett fiberoptiskt mediakonverterarsystem kapabelt att konvertera signaler från Universal Serial Bus (USB) 3.2 och 2.0 mellan elektriska och optiska medium. Nyttan av ett sådant system kan materialiseras i till exempel en utökning av avstånden Universal Serial Bus kan användas. Scenarion som kan gagnas av en sådan utökning av avstånd är till exempel industritillämpningar, mediaproduktion eller elektromagnetiskt brusiga miljöer. För närvarande existerar det fiberoptiska mediakonverterarsystem som är kapabla att konvertera Universal Serial Bus 2.0 samt det långsammaste läget av Universal Serial Bus 3.2 men inte de snabbare lägena av Universal Serial Bus 3.2. Konverteringen och sändandet av dessa lägen med högre datahastigheter med bibehållen kapacitet för det långsamma läget samt Universal Serial Bus 2.0, är vad detta examensarbete undersökt. Arbetet behölls på en teoretisk nivå och tar hänsyn till elektronik, fiberoptik, datastrukturer, nätverksteknik samt systemdesign. Denna rapport presenterar allmänna beaktanden och utmaningar med att designa och konstruera ett fiberoptiskt mediakonverterarsystem i fråga. Utmaningar såsom konvertering av halv-duplex till full-duplex för att kunna skicka och mottaga Universal Serial Bus 2.0 över ett optiskt medium, propagationfördröjningar, transmission av enkeländade nollor samt det låghastighetsprotokoll som används av Universal Serial Bus 3.2. Efter att allmänna beaktanden samt utmaningar har presenterats, läggs två olika förslag fram på arkitekturer för mediakonverterare. De två arkitekturerna är parallell samt seriell. Deras respektive grundläggande struktur redogörs för och de diskuteras sedan med hänsyn till deras specifika utmaningar, styrkor och svagheter. Slutsatsen är att eftersom det inte finns några grundläggande tekniska hinder, är det rimligt att kunna implementera båda arkitekturerna. Slutsatsen är också att den parallella arkitekturen är den enklare att implementera. Detta på grund utav en mer kapabel och komplex optisk modul som därmed reducerar implementationsinsatsen för den parallella arkitekturen, då den kräver mindre komplexa konverteringar än vad den seriella arkitekturen kräver.

The research initiatives addressed in this thesis are geared towards improving the performance of passive optical networks (PONs) through the development of advanced dynamic bandwidth allocation (DBA) protocols. In particular, the aim of the research undertaken is to enhance the quality of service (QoS) offered by standard PONs by means of providing subscribers with service level agreement (SLA) to fulfil applications and associated bandwidth requirements on demand. To accomplish the research objectives, a novel service and bandwidth focused DBA protocol is developed for standard time division multiplexing (TDM), gigabit-capable PONs (GPONs) by flexibly assigning a guaranteed minimum bandwidth to each optical network unit (ONU),terminated at subscribers premises. Modelling and simulation of the developed algorithms have displayed a tenfold enhancement in network performance, showing a superior performance to other published DBA protocols, in terms of mean packet delay. To accomplish protocol optimisation, the ONU upstream transmission properties of TDM-PONs have been further analysed and subsequently the ONU data transfer order in each communication cycle has been dynamically configured to increase the network upstream throughput by overlapping the upstream transmission period with parts of the bandwidth request-allocation process between OLT and ONUs. In addition, with the objective of extending the application of the developed protocol to long-reach PONs by means of reducing the augmented propagation delays due to the network’s extensive reach, the concept of virtual communication cycles has been incorporated into the optimised DBA algorithm. This approach demonstrates comparable transmission efficiency in the context of subscriber throughput and packet delay as in a standard PON but at much longer distances from the network exchange. To overcome the inevitably limited communication capacity of single wavelength TDM protocols and with the transportation of the ever increasing, time-sensitive, multi-media services in mind, a novel multi-wavelength DBA protocol is then developed to be applied to a wavelength division multiplexing–PON. With this protocol, both the downstream and upstream network capacity is dynamically adjusted according to subscribers’ service level and bandwidth demand in each polling cycle as opposed to a fixed upstream network capacity in TDM-PONs. It therefore also demonstrates improved upstream transmission efficiency.

The NetCOPE framework has proven itself as a viable framework for rapid development of hardware accelerated wire-speed network applications using Network Functions Virtualization (NFV). To meet the current and future requirements of such applications the NetCOPE platform has to catch up with upcoming 400 Gigabit Ethernet. Otherwise, it may become deprecated in following years. Catching up with 400 Gigabit Ethernet brings many challenges bringing necessity of completely different way of thinking. Multiple network packets have to be processed each clock cycle requiring a new concept of processing. Advanced memory management is used to ensure constant memory complexity with respect to the number of DMA channels without any impact on performance. Thanks to that, even more than 256 completely independent DMA channels are feasible with current technology. A lot of effort was made to create the framework as generic as possible allowing deployment of 400 Gigabit Ethernet and beyond. Emphasis is put on communication between the framework and host computer via PCI Express technology. Multiple Ethernet ports are also considered. The proposed system is prepared to be deployed on the family of COMBO cards, used as a reference platform.

This work covers the implementation of a raw Ethernet communication module for the Open MPI message passing library. Thereby it focuses on both the reduction of the communication latency for small messages and maximum possible compatibility. Especially the need for particular network devices, adapted network device drivers or kernel patches is avoided. The work is divided into three major parts: First, the networking subsystem of the version 2.6 Linux kernel is analyzed. Second, an Ethernet protocol family is implemented as a loadable kernel module, consisting of a basic datagram protocol (EDP), providing connection-less and unreliable datagram transport, and a streaming protocol (ESP), providing connection-oriented, sequenced and reliable byte streams. The protocols use the standard device driver interface of the Linux kernel for data transmission and reception. Their services are made available to user-space applications through the standard socket interface. Last, the existing Open MPI TCP communication module is ported atop the ESP. With bare EDP/ESP sockets a message latency of about 30 us could be achieved for small messages, which compared to the TCP latency of about 40 us is a reduction of 25 %.