The thesis work concentrated on the developments of selection strategies for the observation of MSSM Higgs bosons in the context of the CMS experiment. The thesis shows, by an example with a MSSM (Minimal Supersymmetric Standard Model) Higgs decaying into two tau, how to define the trigger strategy. The method can be applied for any final state.

The thesis work concentrated on the developments of selection strategies for the observation of MSSM Higgs bosons in the context of the CMS experiment. The thesis shows, by an example with a MSSM (Minimal Supersymmetric Standard Model) Higgs decaying into two tau, how to define the trigger strategy. The method can be applied for any final state.

Syftet med denna studie är att belysa hur tre läromedel för årskurs 1 i matematik väljer att introducera addition och subtraktion. Syftet är också att belysa hur läromedlen synliggör möjligheterna för eleverna att utveckla sin förståelse för sambandet mellan addition och subtraktion. En kvalitativ metod har använts där innehållet i läromedlen, inklusive lärarhandledning, har analyserats utifrån valda delar av HLT-modellen, som är en hypotetisk inlärningsbana. Resultaten visar att de tre olika läromedlen introducerar addition och subtraktion på tre olika sätt. Favorit matematik fokuserar först på att lära eleverna additionskunskaper, sedan fokus på subtraktionskunskap för att sedan jobba med räknesätten lite tillsammans. Singma introducerar addition i ett kapitel för att i nästa kapitel introducera subtraktion. I kapitlet därefter introducerar de sambandet mellan räknesätten. Rik matematik introducerar båda räknesätten i samma kapitel. Vidare visar resultaten att de tre läromedlens fokus för att synliggöra sambandet av räknesätten ligger på olika delar av HLT-modellens steg men att det inte i något av läromedlen använder sig av ångrakonceptet. Detta kan leda till att elever får bristande kunskaper att koppla subtraktion till addition och uppnå flyt med grundläggande subtraktionskombinationer.

The ATLAS experiment pushes the leading edge of experimental particle physics. Increasingly complex hardware, however, brings increasingly complex problems which manifest themselves not only in the detector, but also within the software which drives the detector. The magnitude of the expected interaction rate, too, adds enormous stress to the detector system and the software trigger. In order to prepare the software for these challenges, various detector quantities are considered which may provide debugging handles and robustness against detector problems arising in the ATLAS calorimeter trigger. The effect of electronics noise suppression on these quantities is studied and a brief study of the software trigger performance is followed by recommendations for the implementation of robustness checks.

Made available in DSpace on 2016-04-27T16:57:08Z (GMT). No. of bitstreams: 1 Denilson Goncalves Pereira.pdf: 7924777 bytes, checksum: 477a51645572c92238dd48b6a98b1d8e (MD5) Previous issue date: 2011-05-26 / Secretaria da Educação do Estado de São Paulo / The present work is part of a project that aims to examine how teaching proposal in the classroom can be organized and developed, exploring the everyday contexts in other areas of knowledge and of mathematics itself, with a view to building some expectations learning. Our research involves three mathematics teachers from public schools in São Paulo, each one with a class of Grade 3 High School, during the night, totaling 122 students. The guest teachers work in school EE Padre Anchieta located in Diadema (SP). The project aims to contribute to the professional development of teachers in a consistent manner which is intended to be his practice in the classroom, through a strategy of closely linking theory, teaching practice and research. Through the collaborative work and the hypothetical learning trajectory (HLT), we believe that teachers can reflect about their teaching practice, focusing on a teaching strategy in which the student is motivated to investigate and assign meaning to their learning autonomously. After the teachers know the whole project and the primary HLT by the teacher researcher, with assistance from teachers applicators, that develop a course in class. During this stage, the researcher observed and recorded with audio recordings and notes, teachers reported applicators, along with the protocols of the students, which occurred in each proposed activity, pointing out the mistakes, difficulties, interactions, assumptions that were questioned in elaboration of the trajectory and other observations / O presente trabalho faz parte de um projeto que tem por objetivo analisar o modo como podem ser organizadas e desenvolvidas propostas didáticas em sala de aula, explorando contextos do cotidiano, de diversas áreas de conhecimento e da Matemática, com vistas a contemplar algumas expectativas de aprendizagem. Nossa pesquisa envolve três professores de Matemática da rede pública estadual paulista, cada qual com uma turma da terceira série do Ensino Médio, período noturno, totalizando 122 alunos. Os professores convidados atuam na E.E. Padre Anchieta, localizada em Diadema. O projeto visa a contribuir para o desenvolvimento profissional dos professores de forma coerente com o que se pretende que seja sua prática em sala de aula, mediante uma estratégia de estreita articulação entre teoria, prática docente e pesquisa. Por meio de uma trajetória hipotética de aprendizagem (THA) e do trabalho colaborativo, acreditamos que o professor pode refletir sobre sua prática docente, privilegiando uma estratégia de ensino na qual o aluno seja motivado a investigar e atribuir significado a sua aprendizagem de forma autônoma. A THA preliminar foi elaborada pelo professor pesquisador, com a contribuição dos professores aplicadores, e cada um destes a desenvolveu em uma turma. Nessa etapa, o pesquisador fez observações e registro, por meio de gravações de áudio e anotações, enquanto os professores aplicadores relataram, junto com os protocolos dos alunos, o que ocorreu em cada atividade proposta, apontando os erros, dificuldades, interações, hipóteses que foram questionadas na elaboração da trajetória, além de outras observações

La thèse porte sur l'impact d'optimisations algorithmiques pour la synthèse automatique HLS pour ASIC. Ces optimisations algorithmiques sont des transformations de haut niveau, qui de part leur nature intrinsèque restent hors de porter des compilateurs modernes, même les plus optimisants. Le but est d'analyser l'impact des optimisations et transformations de haut niveau sur la surface, la consommation énergétique et la vitesse du circuit ASIC. Les trois algorithmes évalués sont les filtres non récursifs, les filtres récursifs et un algorithme de détection de mouvement. Sur chaque exemple, des gains ont été possibles en vitesse et/ou en surface et/ou en consommation. Le gain le plus spectaculaire est un facteur x12.6 de réduction de l'énergie tout en maitrisant la surface de synthèse et en respectant la contrainte d'exécution temps réel. Afin de mettre en perspective les résultats (consommation et vitesse), un benchmark supplémentaire a été réalisé sur un microprocesseur ST XP70 avec extension VECx, un processeur ARM Cortex avec extension Neon et un processeur Intel Penryn avec extensions SSE. / The thesis deals with the impact of algorithmic transforms for HLS synthesis for ASIC. These algorithmic transforms are high level transforms that are beyond the capabilities of modern optimizing compilers. The goal is to analyse the impact of the High level transforms on area execution time and energy consumption. Three algorithms have been analyzed: non recursive filters, recursive filter and a motion detection application. On each algorithm, the optimizations and transformations lead to speedups and area/surface gains. The most impressive gain in energy reduction is a factor x12.6, while the area remains constant and the execution time smaller than the real-time constraint. A benchmark has been done on SIMD general purpose processor to compare the impact of the high level transforms: ST XP70 microprocessor with VECx extension, ARM Cortex with Non extension and Intel Penryn with SSE extension.