Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in the early 90s as an alternative to the Schottky barrier diode (SBD) technology for microwave detector applications due to its highly stable temperature characteristics. The ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a thin barrier, which enables RF detection at zero bias from microwaves up to submillimetre wave frequencies. In this work, two heavily doped GaAs contact layer on top and bottom layers adjacent to lightly doped GaAs intermediate layers, enclose undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that acts as a tunnel barrier. The ultimate ambition of this work was to develop a MMIC detector as well as a frequency source based on optimized ASPAT diodes for millimetre wave (100GHz) applications. The effect of material parameter and dimensions on the ASPAT source performances was described using an empirical model for the first time. Since this is a new device, keys challenges in this work were to improve DC and RF characteristic as well as to develop a repeatable, reproducible, and ultimately manufacturable fabrication process flow. This was investigated using two approaches namely air-bridge and dielectric-bridge fabrication process flows. Through this work, it was found that the GaAs/AlAs heterostructures ASPAT diode are more amenable to the dielectric-bridge technique as large-scale fabrication of mesa area up to 4×4Âμm2 with device yields exceeding 80% routinely produced. The fabrication of the ASPAT using i-line optical lithography which has the capability to reduce emitter area to 4×4Âμm2 to lower down the device capacitance for millimetre wave application has been made feasible in this work. The former challenge was extensively studied through materials and structural characterisations by a SILVACO physical modelling and confirmed by comparison with experimental data. The I-V characteristic of the fabricated ASPAT demonstrated outstanding scalability, demonstrating robust processing. A fair comparison has been made between ASPAT and SBD fabricated in-house; indicating ASPAT is extremely stable to the temperature. The RF characterisations were carried out with the aid of Keysight ADS software. The DC characteristic from fabricated GaAs/AlAs ASPAT diodes were absorbed into an ADS simulation tool and utilized to demonstrate the performance of MMIC 100GHz detector as well as 20GHz/40GHz signal generators. Zero bias ASPAT with mesa area of 4×4Âμm2 with video resistance of 90KΩ, junction capacitance of 23fF and curvature coefficient of 23V-1 has demonstrated detector voltage sensitivity above 2000V/W, while the signal source conversion loss and conversion efficiency are 28dB and 0.3% respectively. An estimate noise equivalent power (NEP) for this particular device is 18.8pW/Hz1/2.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

At present, focus of the SiC crystal growth development is on improving the crystalline quality without polytype inclusions, micropipes and the occurrence of extended defects. The purity of the grown material, as well as intentional doping must be well controlled and the processes understood. High-quality substrates will significantly improve device performance and yield. One of the aims of the thesis is further understanding of polytype inclusion formation as well as impurity control in SiC bulk crystals grown using PVT method also termed seeded sublimation method. Carbonization of the source was identified as a major reason behind the polytype inclusion occurrence during the growth. The aim of this work was further understanding of sublimation growth process of 4H-SiC bulk crystals in vacuum, in absence of an inert gas. For comparison growth in argon atmosphere (at 5 mbar) was performed. The effect of the ambient on the impurity incorporation was studied for different growth temperatures. For better control of the process in vacuum, tantalum as a carbon getter was utilized. The focus of the SiC part of the thesis was put on further understanding of the PVT epitaxy with an emphasis on the high growth rate and purity of grown layers. High resistivity 4H-SiC samples grown by sublimation with high growth rate were studied. The measurements show resistivity values up to high 104 cm. By correlation between the growth conditions and SIMS results, a model was applied in which it is proposed that an isolated carbon vacancy donor-like level is a possible candidate responsible for compensation of the shallow acceptors in p-type 4H-SiC. A relation between cathodoluminescence (CL) and DLTS data is taken into account to support the model. To meet the requirements for high voltage blocking devices such as high voltage Schottky diodes and MOSFETs, 4H-SiC epitaxial layers have to exhibit low doping concentration in order to block reverse voltages up to few keV and at the same time have a low on-state resistance (Ron). High Ron leads to enhanced power consumption in the operation mode of the devices. In growth of thick layers for high voltage blocking devices, the conditions to achieve good on-state characteristics become more challenging due to the low doping and pronounced thicknesses needed, preferably in short growth periods. In case of high-speed epitaxy such as the sublimation, the need to apply higher growth temperature to yield the high growth rate, results in an increased concentration of background impurities in the layers as well as an influence on the intrinsic defects. On-state resistance Ron estimated from current density-voltage characteristics of Schottky diodes on thick sublimation layers exhibits variations from tens of mΩ.cm2 to tens of Ω.cm2 for different doping levels. In order to understand the occurrence of high on-state resistance, Schottky barrier heights were first estimated for both forward and reverse bias with the application of thermionic emission theory and were in agreement with literature reported values. Decrease in mobility with increasing temperature was observed and its dependencies of T–1.3 and T–2.0 for moderately doped and low doped samples, respectively, were estimated. From deep level measurements by Minority Carrier Transient Spectroscopy (MCTS), an influence of shallow boron related levels and D-center on the on-state resistance was observed, being more pronounced in low doped samples. Similar tendency was observed in depth profiling of Ron. This suggests a major role of boron in a compensation mechanism. In the second part of the thesis growth and characterization of GaN is presented. Excellent electron transport properties with high electron saturate drift velocity make GaN an excellent candidate for electronic devices. Especially, AlGaN/GaN based high electron mobility transistors (HEMT) have received an increased attention in last years due to their attractive properties. The presence of strong spontaneous and piezoelectric polarization due to the lattice mismatch between AlGaN and GaN is responsible for high free electrons concentrations present in the vicinity of the interface. Due to the spatial separation of electrons and ionized donors or surface states, 2DEG electron gas formed near the interface of the heterostructure exhibits high sheet carrier density and high mobility of electrons. Al0.23Ga0.77N/GaN based HEMT structures with an AlN exclusion layer on 100 mm semiinsulating 4H-SiC substrates have been grown by hot-wall MOCVD. The electrical properties of the two-dimensional electron gas (2DEG) such as electron mobility, sheet carrier density and sheet resistance were obtained from Hall measurements, capacitance-voltage and contact-less eddy-current techniques. The effect of different scattering mechanisms on the mobility have been taken into account and compared to the experimental data. Hall measurements were performed in the range of 80 to 600 K. Hall electron mobility is equal to 17140 cm2(Vs)-1 at 80 K, 2310 cm2(Vs)-1 at room temperature, and as high as 800 cm2(Vs)-1 at 450 K, while the sheet carrier density is 1.04x1013 cm-2 at room temperature and does not vary very much with temperature. Estimation of different electron scattering mechanisms reveals that at temperatures higher than room temperature, experimental mobility data is mainly limited by optical phonon scattering. At relevant high power device temperature (450 K) there is still an increase of mobility due to the AlN exclusion layer. We have studied the behaviour of Ga-face GaN epilayers after in-situ thermal treatment in different gas mixtures in a hot-wall MOCVD reactor. Influence of N2, N2+NH3 and N2+NH3+H2 ambient on the morphology was investigated in this work. The most stable thermal treatment conditions were obtained in the case of N2+NH3 gas ambients. We have also studied the effect of the increased molar ratio of hydrogen in order to establish proper etching conditions for hot-wall MOCVD growth.

High power Gallium Nitride (GaN) based field effect transistors are used in many high power applications from RADARs to communications. These devices dissipate a large amount of power and sustain high electric fields during operation. High power dissipation occurs in the form of heat generation through Joule heating which also results in localized hot spot formation that induces thermal stresses. In addition, because GaN is strongly piezoelectric, high electric fields result in large inverse piezoelectric stresses. Combined with residual stresses due to growth conditions, these effects are believed to lead to device degradation and reliability issues. This work focuses on studying these effects in detail through modeling of Heterostructure Field Effect Transistors (HFETs) and metal oxide semiconductor hetero-structure field effect transistor (MOSHFETs) under various operational conditions. The goal is to develop a thorough understanding of device operation in order to better predict device failure and eventually aid in device design through modeling. The first portion of this work covers the development of a continuum scale model which couples temperature and thermal stress to find peak temperatures and stresses in the device. The second portion of this work focuses on development of a micro-scale model which captures phonon-interactions at the device scale and can resolve local perturbations in phonon population due to electron-phonon interactions combined with ballistic transport. This portion also includes development of phonon relaxation times for GaN. The model provides a framework to understand the ballistic diffusive phonon transport near the hotspot in GaN transistors which leads to thermally related degradation in these devices.

Fabrication of artificially structured superlattices, when controlled on a nanoscale level, can exhibit enhanced dielectric properties over a wide temperature range. Possible fabrication of new functional devices based on the parametric values of dielectric constants of these heterostructures was the major motivation behind the work. Chapter 1 gives a brief overview of ferroelectrics; their defining features and their commercial importance to electronic industry. An introduction to ferroelectric superlattices, their technological application and fundamental physics that influence the behavior of superlattices are provided. Chapter 2 deals with the various experimental studies carried out in this research work. It gives the details of the experimental set up and the basic operation principles of various structural and physical characterizations of the materials prepared. A brief explanation of material fabrication, structural, micro structural and physical property measurements is discussed. Chapter 3 involves fabrication of two-component ferroelectric superlattices consisting of Barium Titanate (BTO), and Strontium Titanate (STO) with nanoscale control of superlattice periodicities by high-pressure multi target pulsed laser deposition on Pt (111)/Ti/SiO2/Si (100) substrate. Superlattices with varying periodicities were fabricated and their compositional variation across the thin film and the interface width were studied using Secondary Ion Mass Spectrometry (SIMS). Fabrications of superlattice structure were supported by observation of satellite peaks in XRD corresponding to the coherent heterostructures. The microstructural analysis was carried out using cross-sectional scanning electron microscopy (SEM), and contact mode-AFM was used to image surface morphology and root-mean-square (rms) roughness of the thin film heterostructure. Chapter 4 deals with ferroelectric studies of BTO/STO superlattices. The size dependent polarization behaviors of the superlattices are shown. The experimental realization of the dimensional range in which, the long-range coupling interaction dominates the overall polarization behavior of the system was studied. The dependence of average spontaneous polarization on the individual layer thickness, temperature and the dimensional range of interaction are discussed. The enhanced non-linear behaviors of the films were measured in terms of tunability. The dielectric phase transition behavior of superlattice structures of different periodicities was studied. Chapter 5 focuses on fabrication of three-component ferroelectric superlattices consisting of Barium Titanate (BTO), Calcium Titanate (CTO) and Strontium Titanate (STO). The fabrications of superlattice structures were confirmed by the presence of satellite reflections in XRD analysis and a periodic concentration of Sr, Ba and Ca throughout the film in Depth profile of SIMS analysis. The microstructural analysis was carried out using cross-sectional scanning electron microscopy (SEM), and contact mode-AFM was used to image surface morphology and root-mean-square (rms) roughness of the thin film heterostructure. The dielectric characteristic and polarization properties of the system are discussed. Large variations of lattice distortion in the consisting layers were achieved by varying the stacking sequence and superlattice periodicity. The influence of interfacial strain on enhancement of ferroelectric polarization was studied. The size dependence and the role of interfaces in the observed enhancements of the dielectric behaviors were highlighted. The tunability of about 55% was achieved in these systems and was higher than any of the single polycrystalline thin film of the constituent materials reported till date. The enhanced dielectric properties were thus discussed in terms of the interfacial strain driven polar region due to high lattice mismatch and electrostatic coupling due to polarization mismatch between individual layers. Chapter 6 deals with the dielectric response, impedance spectroscopy and the DC leakage characteristics of the superlattice structures. All the heterostructures fabricated, exhibited low frequency dispersion, similar to that of the Jonscher’s universal type of relaxation behavior. The anomalous dispersion was observed in the imaginary dielectric constant at high frequencies. A Debye type relaxation behavior was observed in the impedance analysis at low temperatures, whereas, a departure from ideal ‘Debye’ type was noticed as the temperature was increased. The leakage currents of all the heterostructures were found to be a few orders less than the homogeneous single layer thin films. A space charge limited conduction was observed in al the superlattice structures fabricated. Chapter 7 summarizes the present study and discusses about the future work that could give more insight into the understanding of the ferroelectric perovskite heterostructures.

This work investigates the defect energies, band alignments, and charge carrier recombination in polycrystalline Cu(In1-xGax)(Se1-ySy)2 chalcopyrite thin films and the interrelationship with the alloy composition. Photoluminescence spectroscopy of investigated Cu-poor Cu(In,Ga)(Se,S)2 layers generally shows broad emission lines with the corresponding maxima shifting towards higher energies under decreasing temperature or under increasing excitation power. Admittance spectroscopy of Cu-poor ZnO/CdS/Cu(In,Ga)(Se,S)2 chalcopyrite devices shows that the activation energies of the dominant defect distributions involving donors at the CdS/absorber interface and deep acceptors in the chalcopyrite bulk, increase upon alloying CuInSe2 with S. The band alignments within the Cu(In1-xGax)(Se1-ySy)2 system are determined using the energy position of the bulk acceptor state as a reference. The band gap enlargement under Ga alloying is accommodated almost exclusively in the rise of the conduction band edge, whereas the increase of band gap upon alloying with S is shared between comparable valence and conduction band offsets. The extrapolated band discontinuities [delta]EV(CuInSe2/CuInS2) = -0.23 eV, [delta]EC(CuInSe2/CuInS2) = 0.21 eV, [delta]EV(CuInSe2/CuGaSe2) = 0.036 eV, and [delta]EC(CuInSe2/CuGaSe2) = 0.7 eV are in good agreement with theoretical predictions. Current-voltage analysis of Cu-poor ZnO/CdS/Cu(In,Ga)(Se,S)2 devices reveals recombination barriers which follow the band gap energy of the absorber irrespective of alloy composition, as expected for dominant recombination in the chalcopyrite bulk. In turn, the recombination at the active junction interface prevails in Cu-rich devices which display substantially smaller barriers when compared to the band gap energy of the absorber. The result indicates that the Cu-stoichiometry is the driving compositional parameter for the charge carrier recombination in the chalcopyrite heterojunctions under investigations.

In the present work a Metal / organic / inorganic semiconductor hybrid heterostructure (Ag / DiMe−PTCDI / GaAs) was built under UHV conditions and characterised in situ. The aim was to investigate the influence of the organic layer in the surface properties of GaAs(100) and in the electrical response of organic−modified Ag / GaAs Schottky diodes. The device was tested by combining surface−sensitive techniques (Photoemission spectroscopy and NEXAFS) with electrical measurements (current−voltage, capacitance−voltage, impedance and charge transient spectroscopies). Core level examination by PES confirms removal of native oxide layers on sulphur passivated (S−GaAs) and hydrogen plasma treated GaAs(100) (H+GaAs) surfaces. Additional deposition of ultrathin layers of DiMe−PTCDI may lead to a reduction of the surface defects density and thereby to an improvement of the electronic properties of GaAs. The energy level alignment through the heterostructure was deduced by combining UPS and I−V measurements. This allows fitting of the I−V characteristics with electron as majority carriers injected over a barrier by thermionic emission as a primary event. For thin organic layers (below 8 nm thickness) several techniques (UPS, I−V, C−V, QTS and AFM) show non homogeneous layer growth, leading to formation of voids. The coverage of the H+GaAs substrate as a function of the nominal thickness of DiMe−PTCDI was assessed via C−V measurements assuming a voltage independent capacitance of the organic layer. The frequency response of the device was evaluated through C−V and impedance measurements in the range 1 kHz−1 MHz. The almost independent behaviour of the capacitance in the measured frequency range confirmed the assumption of a near geometrical capacitor, which was used for modelling the impedance with an equivalent circuit of seven components. From there it was found a predominance of the space charge region impedance, so that A.C. conduction can only takes place through the parallel conductance, with a significant contribution of the back contact. Additionally a non linear behaviour of the organic layer resistance probably due to the presence of traps was deduced. ( ) ω ' R QTS measurements performed on the heterostructure showed the presence of two relaxations induced by deposition of the organic layer. The first one is attributed to the presence of a deep trap probably located at the metal / organic interface, while the second one has very small activation energy ( ~ 20 meV) which are probably due to disorder at the organic film. Those processes with small activation energies proved to be determinant for fitting the I−V characteristics of DiMe−PTCDI organic modified diodes using the expressions of a trapped charge limited current regime TCLC. Such a model was the best analytical approach found for fitting the I−V response. Further improving probably will involve implementation of numerical calculations or additional considerations in the physics of the device.

The present work has been focused on the growth of Group III-nitride epitaxial layers and nanostructures on Si (111) substrates by plasma-assisted molecular beam epitaxy. Silicon is regarded as a promising substrate for III-nitrides, since it is available in large quantity, at low cost and compatible to microelectronics device processing. However, three-dimensional island growth is unavoidable for the direct growth of GaN on Si (111) because of the extreme lattice and thermal expansion coefficient mismatch. To overcome these difficulties, by introducing β-Si3N4 buffer layer, the yellow luminescence free GaN can be grow on Si (111) substrate. The overall research work carried out in the present study comprises of five main parts. In the first part, high quality, crack free and smooth surface of GaN and InN epilayers were grown on Si(111) substrate using the substrate nitridation process. Crystalline quality and surface roughness of the GaN and InN layers are extremely sensitive to nitridation conditions such as nitridation temperature and time. Raman and PL studies indicate that the GaN film obtained by the nitridation sequences has less tensile stress and optically good. The optical band gaps of InN are obtained between ~0.73 to 0.78 eV and the blueshift of absorption edge can be induced by background electron concentration. The higher electron concentration brings in the larger blueshift, due to a possible Burstein–Moss effect. InN epilayers were also grown on GaN/Si(111) substrate by varying the growth parameters such as indium flux, substrate temperature and RF power. In the second part, InGaN/Si, GaN/Si3N4/n-Si and InN/Si3N4/n-Si heterostructures were fabricated and temperature dependent electrical transport behaviors were studied. Current density-voltage plots (J-V-T) of InGaN/Si heterostructure revealed that the ideality factor and Schottky barrier height are temperature dependent and the incorrect values of the Richardson’s constant produced, suggests an inhomogeneous barrier at the heterostructure interface. The higher value of the ideality factor compared to the ideal value and its temperature dependence suggest that the current transport is primarily dominated by thermionic field emission rather than thermionic emission. The valence band offset of GaN/β-Si3N4/Si and InGaN/Si heterojunctions were determined by X-ray photoemission spectroscopy. InN QDs on Si(111) substrate by droplet epitaxy and S-K growth method were grown in the third part. Single-crystalline structure of InN QDs (droplet epitaxy) was verified by TEM and the chemical bonding configurations of InN QDs were examined by XPS. The interdigitated electrode pattern was created and (I-V) characteristics of InN QDs were studied in a metal–semiconductor–metal configuration in the temperature range of 80–300 K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. A systematic manipulation of the morphology, optical emission and structural properties of InN/Si (111) QDs (S-K method) is demonstrated by changing the growth kinetics parameters such as flux rate and growth time. The growth kinetics of the QDs has been studied through the scaling method and observed that the distribution of dot sizes, for samples grown under varying conditions, has followed the scaling function. In the fourth part, InN nanorods (NRs) were grown on Si(111) and current transport properties of NRs/Si heterojunctions were studied. The rapid rise and decay of infrared on/off characteristics of InN NRs/Si heterojunction indicate that the device is highly sensitive to the IR light. Self-aligned GaN nanodots were grown on semi-insulating Si(111) substrate. The interdigitated electrode pattern was created on nanodots using photolithography and dark as well as UV photocurrent were studied. Surface band gaps of InN QDs were estimated from scanning tunneling spectroscopy (STS) I-V curves in the last part. It is found that band gap is strongly dependent on the size of InN QDs. The observed size-dependent STS band gap energy blueshifts as the QD’s diameter or height was reduced.

The popularity of III-nitride materials has taken up the semiconductor industry to newer applications because of their remarkable properties. In addition to having a direct and wide band gap of 3.4 eV, a very fascinating property of GaN is the band gap tuning from 0.7 to 6.2 eV by alloying with Al or In. The most common orientation to grow optoelectronic devices out of these materials are the polar c-plane which are strongly affected by the intrinsic spontaneous and piezoelectric polarization fields. Devices grown in no polar orientation such as (1 0 –1 0) m-plane or (1 1 –2 0) a-plane have no polarization in the growth direction and are receiving a lot of focus due to enhanced behaviour. The first part of this thesis deals with the development of non-polar epimGaN films of usable quality, on an m-plane sapphire by plasma assisted molecular beam epitaxy. Growth conditions such as growth temperature and Ga/N flux ratio were tuned to obtain a reasonably good crystalline quality film. MSM photodetectors were fabricated from (1 0 -1 0) m-GaN, (1 1 -2 0) a-GaN and semipolar (1 1 -2 2) GaN films and were compared with the polar (0 0 0 2) c-GaN epilayer. Later part of the thesis investigated (1 0 -1 0) InN/ (1 0 -1 0) GaN heterostructures. Further, we could successfully grow single composition nonpolar a-plane InxGa1-xN epilayers on (1 1 -2 0) GaN / (1 -1 0 2) sapphire substrate. This thesis focuses on the growth and characterisation of nonpolar GaN, InxGa1-xN and InN by plasma assisted molecular beam epitaxy and on their photodetection potential. Chapter 1 explains the motivation of this thesis work with an introduction to the III-nitride material and the choice of the substrate made. Polarization effect in the polar, nonpolar and semipolar oriented growth is discussed. Fabrication of semiconductor photodetectors and its principle is explained in details. Chapter 2 discusses the various experimental tools used for the growth and characterisation of the film. Molecular beam epitaxy technique is elaborately explained along with details of the calibration for the BEP of various effusion cells along with growth temperature at the substrate. Chapter 3 discusses the consequence of nitridation on bare m-sapphire substrate. Impact of nitridation step prior to the growth of GaN film over (1 0 -1 0) m-sapphire substrate was also studied. The films grown on the nitridated surface resulted in a nonpolar (1 0 -1 0) orientation while without nitridation caused a semipolar (1 1 -2 2) orientation. Room temperature photoluminescence study showed that nonpolar GaN films have higher value of compressive strain as compared to semipolar GaN films, which was further confirmed by room temperature Raman spectroscopy. The room temperature UV photodetection of both films was investigated by measuring the I-V characteristics under UV light illumination. UV photodetectors fabricated on nonpolar GaN showed better characteristics, including higher external quantum efficiency, compared to photodetectors fabricated on semipolar GaN. Chapter 4 focuses on the optimization and characterisation of nonpolar (1 0 -1 0) m-GaN on m-sapphire by molecular beam epitaxy. A brief introduction to the challenges in growing a pure single phase nonpolar (1 0 -1 0) GaN on (1 0 -1 0) sapphire without any other semipolar GaN growth is followed by our results achieving the same. Effect of the growth temperature and Ga/N ratio on the structural and optical properties of m-GaN epilayers was studied and the best condition was obtained for the growth temperature of 7600C and nitrogen flow of 1 sccm. Strain in the film was quantitatively measured using Raman spectroscopy and qualitatively analyzed by RSM. Au/ nonpolar GaN schottky diode was fabricated and temperature dependent I-V characteristics showed rectifying nature. Chapter 5 demonstrates the growth of (1 0 -1 0) m-InN / (1 0 -1 0) m-GaN / (1 0 -1 0) m-sapphire substrate. Nonpolar InN layer was grown at growth temperature ranging from 3900C to 440C to obtain a good quality film at 4000C. An in-plane relationship was established for the hetrostructures using phi-scan and a perfect alignment was found for the epilayers. RSM images on the asymmetric plane revealed highly strained layers. InN band gap was found to be around 0.8 eV from absorption spectra. The valance band offset value is calculated to be 0.93 eV for nonpolar m-plane InN/GaN heterojunctions. The heterojunctions form in the type-I straddling configuration with a conduction band offsets of 1.82 eV. Chapter 6 focuses on the optimization of nonpolar (1 1 -2 0) a-GaN on (1 -1 0 2) r-sapphire by molecular beam epitaxy. Effect of the growth temperature and Ga/N ratio on the structural and optical properties of a-GaN epilayers was studied and the best condition was obtained for the growth temperature of 7600C and nitrogen flow of 1 sccm. An in-plane orientation relationship is found to be [0 0 0 1] GaN || [-1 1 0 1] sapphire and [-1 1 0 0] GaN || [1 1 -2 0] sapphire for nonpolar GaN on r-sapphire substrate. Strain in the film was quantitatively measured using Raman spectroscopy and qualitatively analyzed by RSM. UV photo response of a-GaN film was measured after fabricating an MSM structure over the film with Au. EQE of the photodetectors fabricated in the (0 0 0 2) polar and (1 1 -2 0) nonpolar growth directions were compared in terms of responsively, nonpolar a-GaN showed the best sensitivity at the cost of comparatively slow response time. Chapter 7 demonstrates the growth of non-polar (1 1 -2 0) a-plane InGaN epilayers on a-plane (1 1 -2 0) GaN/ (1 -1 0 2) r-plane sapphire substrate using PAMBE. The high resolution X-ray diffraction (HRXRD) studies confirmed the orientation of the films and the compositions to be In0.19Ga0.81N, In0.21Ga0.79N and In0.23Ga0.77N. The compositions of the films were controlled by the growth parameters such as growth temperature and indium flux. Effect of variation of Indium composition on the strain of the epilayers was analyzed from the asymmetric RSM images. Further, we report the growth of self-assembled non-polar high indium clusters of In0.55Ga0.45N over non-polar (1 1 -2 0) a-plane In0.17Ga0.83N epilayer grown on a-plane (1 1 -2 0) GaN / (1 -1 0 2) r-plane sapphire substrate. The structure hence grown when investigated for photo-detecting properties, showed sensitivity to both infrared and ultraviolet radiations due to the different composition of InGaN region. Chapter 8 concludes with the summary of present investigations and the scope for future work.