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After decades of development, Taiwan¡¦s IC industry has become the world¡¦s third largest manufacturing center, and claimed the positions of the world¡¦s first largest IC foundry industry, second largest packaging industry, as well as second largest IC design industry. For an industry to be successful, in addition to the provision of various niches and resources from private businesses, it requires the coordination of industrial policy-making, peripheral conditions, and infrastructures. Therefore, to enhance current competitive advantages and facilitate industrial transformation for greater competitiveness, the government needs to make effective industrial policy to promote competitive environment. For this reason, this study intends to investigate the current competitive environment of IC industry, how the government responds in terms of stipulating rules and regulations, and what the primary concerns of policy adoption are. It is clear that aside from an effort by businesses, the assistance from government is pivotal to industrial development as well. This study is an attempt to first, collect literature related to industrial analysis and policy; secondly, to analyze the competitive environment of IC industry and thereby find out the relevant policies that influence the managerial effectiveness of Taiwan¡¦s IC industry; and lastly, to survey IC companies and experts on IC industry by utilizing a questionnaire designed based on Fuzzy Analytic Hierarchy Process. After prioritizing the concrete measures for a variety of dimensions of IC industrial policies based on the survey results, the researcher proposes top ten most emphasized including: the assistance in introduction of techniques, the training of technological talented, the aid in the development of SOC technique, the subsidy in R&D of innovative techniques, the accelerated depreciation on R&D equipments, the implementation of three-links, the tariff exemption for importing R&D equipments, the enhancement of National Defense Substitute Servicemen (NDSS), the training of marketing talented, and the enactment of patent rules. Accordingly, this study concluded by providing suggestions for government, IC industry, and future research.

Economic Value Added ¡]EVA¡^to be a business performace indicator popularly. It surveys business¡¦ ability of value creation through tranditional accounting net income and capital opportunity cost. In this study, I focus on IC Design industries¡¦ performance by EVA and use ten years data to examine it. The study purposes as below, A. Does Taiwan IC Design Industry owns ability of value creation for share owners ? B. Find out the factors of Taiwan IC Design Industry¡¦s performance. C. Comment on Taiwan IC Design Industry¡¦s performance in various sub-industries D. Does Taiwan IC Design Industry exist variation in various sub-industries ? E. Find out which sub-industry owns the best efficiency and the lowest volatility in the meanwhile. F. Find out the factors of Taiwan IC Design Industry¡¦s ability of value creation. The study finding as below, A. The standard deviation and quartile deviation of Taiwan IC Design Industry are uniformity and it is implying that the normal distribution and probability distribution are similar. B. About 80% of EVA-Spread of Taiwan IC Design companies are positive, it implies that the ability of value creation of Taiwan IC Design Industry is very well. C. According to evidence-based data, the WACC of Taiwan IC Design Industry is influenced by the cost of equity capital. D. The ROIC of Taiwan IC Design Industry is influenced by Taiwan Semi-conductor Inductry¡¦s ROIC and the real GDP growth rate of Hongkong, China and South Korea. E. The capital turnover of Taiwan IC Design Industry does not link with the ROIC of Taiwan IC Design Industry. F. According to evidence-based data, the variation is exist between Taiwan IC Design Sub-industries. G. The result of regression analysis that past years Invested Capital Growth Rate of sub-industries to be independent variable and EVA-Spreads to be dependent variable implys that the EVA-Spread of Taiwan IC Design Industry is not effected by Invested Capital Growth Rate, then we know that Invested Capital is not the main factor of value creation of Taiwan IC Design Industry. H. The Capital Turnover Rate and the Return Rate of EBIT is the main factors of ROIC, they effected the sub-industries by different levels.

The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010. The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature. The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology. The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.

This study tested the precision and accuracy of a triethanolamine (TEA) absorbent in the OgawaTM Passive Sampling Device (PSD) for detection of ambient hydrogen fluoride (HF). The project was initiated to develop a method to verify compliance with emissions regulations for Coronet. Field and laboratory trials were conducted. Mixed cellulose ester filters were saturated with 70% TEA and placed in the PSDs. Aermod ISCT3 modeled ambient HF concentrations at Coronet to guide deployment of PSDs at 28 sampling stations, 3 PSDs per station, 500 to 3500 meters from Coronet. After 30 days of sampling, ambient HF concentrations were calculated from ion chromatographic (IC) analysis (NIOSH Method 7906/AS14 column) results to be in the low parts per billion (ppb) range. Concentration increased with proximity to Coronet as predicted by Aermod ISCT3. Average precision for collocated PSDs was less than 5%. Laboratory validation of the method used a HF permeation tube in a Teflon and high density polyethylene (HDPE) sampling train with silica-dried ultra zero air and crushed sodium hydroxide (NaOH) reference samplers. PSD accuracy was a constant 23% average and average precision was 32%, dropping 50% with minor procedural improvements. Validated field results verified compliance with HF emissions regulations for Coronet.

With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.

本研究個案公司所屬行業為IC設計，一般而言，IC設計公司致力於研發和設計，而將生產部份交由專業代工廠，個案公司卻在其經營狀況處於高峰之際，令人意外地宣佈準備自建晶圓廠，個案公司是在什麼動機考量下作出這決策？又在如此重大策略之後，真的可以解決個案公司的問題嗎？ 本研究係以個案公司為主要研究對象，敘述個案公司所屬的產業環境及其因應產業變遷、力求公司成長過程中在經營策略上的重大改變，闡述個案公司重大的轉變策略的背景因素，並試圖以財務分析的方法事先洞查該公司將來可能面臨的經營問題，再透過SWOT分析、五力分析來看個案公司經營策略轉變的優劣之處及其可能所帶出的經營結果。 透過本個案分析可以證明跨入非本業專精的經營或嘗試自行取代過去一直依賴的專業外包產能是冒了很大的風險，若無完整的配套策略及財務後盾，反而讓原本體質良好的企業陷入經營困境；最後本研究發現適當的製程外包除可減輕負債、設備折舊壓力，對企業本身的ROA、ROE也可維持較佳的表現；另外企業經營的優劣勝敗取決於是否聚焦在”賺最專業的本業”。 關鍵詞：IC設計、IDM、SWOT、五力分析 / This study analyzes an IC design firm’s decision on whether to build and own a fabrication plant (“fab”). In general, IC design firms outsource the production of chips to independent semiconductor foundries. The case company, however, decided to build its own fab during its peak years of operation. What motivated this business decision? Did the rare industry practice meet the firm’s needs? This case study describes the company’s complex industry environments, its business strategies as the firm was coping with industry trends and managing phenomenal growth, and essential background factors that had led to the “own-a-fab” decision. This study also conducts financial analysis in anticipation with the company’s operational challenges. It uses SWOT and Porter’s five forces analysis so as to delineate the benefits and costs of this major shift in business strategy as well as the business results. The study provides evidence that major risks are taken as firms try to divest into an unfamiliar business area (which in this case was outsourced to professional foundries). Without a well-conceived strategy with corresponding measures and sufficient financial backing, a fine company may run into business troubles. Moreover, this study finds that proper outsourcing of manufacturing processes reduces debt and equipments depreciation pressures while contributing to better ROA and ROE performances. The study concludes that successful businesses should try gain focus on it best, most-skillful expertise areas. Key Words：IC design,IDM,SWOT,Five Forces Model.

In this thesis Direct Numerical Simulation (DNS) is used to investigate the development of turbulent premixed flame kernels during the early stages of growth typical of the period following spark ignition. Two distinct aspects of this phase are considered: the interaction of the expanding kernel with a field of decaying turbulence, and the chemical and thermo-diffusive response of the flame for different fresh-gas compositions. In the first part of the study, three-dimensional, repeated simulations with single-step chemistry are used to generate ensemble statistics of global flame growth. The surface-conditioned mean fluid-velocity magnitude is found to vary significantly across different isosurfaces of the reaction progress variable, and this is shown to lead to a bias in the distribution of the Surface Density Function (SDF) around the developing flame. Two-dimensional simulations in an extended domain indicate that this effect translates into a similar directional bias in the Flame Surface Density (FSD) at later stages in the kernel development. Properties of the fresh gas turbulence decay are assessed from an independent, non-reacting simulation database. In the second part of this study, two-dimensional simulations with a detailed 68-step reaction mechanism are used to investigate the thermo-diffusive response of pure methane-air, and hydrogen-enriched methane-air flames. The changes in local and global behaviour due to the different laminar flame characteristics, and the response of the flames to strain and curvature are examined at different equivalence ratios and turbulence intensities. Mechanisms leading to flame quenching are discussed and the effect of mean flame curvature is assessed through comparison with an equivalent planar flame. The effects of hydrogen addition are found to be particularly pronounced in flame kernels due to the higher positive stretch rates and reduced thermo-diffusive stability of hydrogen-enriched flames.

3D-NoC architectures are the amalgamation of the 3D integration (Die stacking of 3D-IC Technology) with the increased scalability found in NoC. Originally, it was proposed to tackle the problem of increasing the number of cores in the 2D plane which seems incompetent due to long distance interconnects. This architecture is aimed to optimize performance, power consumption, achieve low latency and increase the network bandwidth. Nevertheless, as more dies were being stacked vertically, IC operating frequency increases and this leads to some thermal issues which include high power density which increases average temperature. In addition to that, longer heat dissipation path results in different heat dissipation in each layer of the NoC which worsen the situation. An increase in the overall power consumption increases the average temperature, reduces performance and reliability. In this paper, an adaptive thermal-aware management scheme was proposed for 3D-NoCs, concentrating more on the hotspot regions in the network. This proposed protocol employs the thermal state of intermediate nodes and flits properties in a random uniform distributive way for packet routing. The proposed algorithm increases network availability and tends to distribute the temperature of the system evenly and uniformly within the network and making sure that packets are not forwarded to the hotspot node(s) and only flits with certain properties in the distribution are forwarded to the hotspot node(s). Before or during transmission, these two distributions must be calculated alongside the current node temperature to knowing which state of the distribution that node and flit belong to. The simulation shows this gave better performance in throughput and reliability of the network by reducing the number of hotspot nodes in the NoC. The proposed algorithm also reduces power consumption which is a function of temperature. Simulations show that our proposed algorithm reduces the total power/energy consumed by more than 59\% and throughput is improved by 69\% compared to a traditional XYZ routing. / Graduate