<p>Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.</p><p>Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.</p><p>Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.</p><p>Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.</p><p>In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.</p><p>Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. In addition, the proposed on-chip debug circuitry can identify erroneous segments of observed data by using compact signatures that are stored in the DRAM a priori. Only failing intervals are off-loaded from a temporary trace buffer into DRAM, allowing for a more efficient use of the memory, resulting in a larger observation window.</p><p>In summary, this dissertation provides solutions to several challenges related to 3D test and debug that need to be addressed before volume manufacturing of 3D ICs can be viable.</p> / Dissertation

The unwanted sound, noise, can lead to health problems, e.g. hearing loss and stress-related problems. A pre-knowledge of noise generation by machines is of great importance due to the ever-shorter product development cycles and stricter noise legislation. The noise from a machine radiates to the environment indirectly via the foundation structure and directly via the surrounding fluid. A fluid machine converts the energy from the fluid into mechanical energy or vice versa. Examples of the fluid machines are internal combustion engines (IC-engines), pumps, compressors, and fans. Predicting and controlling noise from a fluid machine requires a model of the noise sources themselves, i.e. acoustic source data. In the duct systems connected to the fluid machines, the acoustic source interacts strongly with the system boundaries, and the source characteristics must be described using in-duct methods. Above a certain frequency, i.e. first non-plane wave mode cut-on frequency, the sound pressure varies over the duct cross-section and non-plane waves are introduced. For a number of applications, the plane wave range dominates and the non-plane waves can be neglected. But for machines connected to large ducts, the non-plane wave range is also important. In the plane wave range, one-dimensional process simulation software can be used to predict, e.g. for IC-engines, the acoustic in-duct source characteristics. The high frequency phenomena with non-plane waves are so complicated, however, that it is practically impossible to simulate them accurately. Thus, in order to develop methods to estimate the sound produced, experimental studies are also essential. This thesis investigates the acoustic in-duct source characterization of fluid machines with applications to exhaust noise from medium speed IC-engines.  This corresponds to large engines used for power plants or on ships, for which the non-plane wave range also becomes important. The plane wave source characterization methods are extended into the higher frequency range with non-plane waves. In addition, methods to determine non-plane wave range damping for typical elements in exhaust systems, e.g. after-treatment devices, are discussed. / <p>QC 20151119</p>

Clock multipliers are among the most critical elements in high speed digital circuits. Power consumption, area, jitter and wide tuning range are key design metrics in these circuits. To provide a wide range of clock frequencies, Digitally Controlled Ring Oscillators (DCROs), whose frequencies are discretely tuned using a Frequency Code Word (FCW), have been investigated in recent studies. They have several advantages over LC-based Voltage Controlled Oscillators (VCO) including simplicity of design, small die area (i.e. no large inductors), better compatibility with deep submicron CMOS processes,ability to offer multiple output phases, and wider tuning range.A compact differential Injection Locked Clock Multiplier (ILCM) based on an injection locked DCRO is implemented in this thesis. As the transistor features continuously shrink and the supply voltage is reduced, ILCMs are becoming more prone to issues such as increased effect of random mismatch, increased device noise, susceptibility of the design to noise coupling and vulnerability to Process Voltage and Temperature (PVT) variations. Furthermore, ILCMs in recent System on a Chip (SoCs) have stringent design requirements including accurate frequency tuning, fine fractional resolution, high levels of integration and better amenability to technology scaling. In the proposed ILCM, multiple techniques were used to address deep submicron CMOS design challenges, as well as modern applications’ requirements. The design is fully digital, synthesizable and automatically placed and routed. All circuit blocks were implemented using digital design flow and designed using a Hardware Description Language (HDL). This allows the design to be more easily ported to deep submicron processes. Online or offline PVT calibration can be performed using a replica oscillator and high speed digital counters to track frequency drifts with PVT variations. A DCRO based on a matrix structure has been utilized to reduce period variations due to random mismatch. The DCRO is built up from pseudo differential delay cells to enhance design immunity to noise coupling. The key thesis contributions are implementing a new DCRO structure using fully syntheziable differential structure, utilizing a novel PVT calibrator that can compensate for frequency mismatch between the main DCRO and its replica, and using a low complexity fractional ILCM technique that achieves a fine fractional resolution with few number of ring oscillator stages.Designed in a TSMC 65 nm GP CMOS process with no analog or RF enhancements, the proposed ILCM frequency ranges from 1.0 to 1.8 GHz and occupies 124:5 m 170 m of chip area. The ILCM can operate in integer or fractional mode for multiplication ratios up to 9. At 1.7 GHz and 1.1 V, the measured integrated RMS jitter (1 kHz to 30 MHz) for the 3rd and 9th multiplication factors are 197 fs and 381 fs, respectively. The ILCM consumes 13.25 mW of power and has a fraction resolution of fref=32. Furthermore, it achieves a jitter-power FOM of −241 dB, when measured at room temperature and 1.1 V. When tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the ILCM. In the presence of voltage variations (from 0.9 V to 1.1 V) and temperature variations (from 30 C to 70 C), the maximum integrated RMS jitter variation observed was 50 fs.

No description available.

Dual fuel combustion is one strategy to achieve low oxides of nitrogen and soot emissions while maintaining the fuel conversion efficiency of IC engines. However, it also suffers from high engine-out carbon monoxide and unburned hydrocarbon emissions, and the incidence of knock at high loads. The present work focused on CFD simulation of diesel-methane dual fuel combustion in a single-cylinder research engine (SCRE). For pure diesel combustion, a load sweep of 2.5 bar brake mean effective pressure (BMEP) to 7.5 bar BMEP was performed at a constant engine speed of 1500 rpm and a diesel injection pressure of 500 bar. For diesel-methane dual fuel combustion, a methane percent energy substitution sweep was performed from 30% to 90 % at 1500 rpm, 3.3 bar BMEP, 500 bar Pinj, and 355 crank angle degrees (CAD) diesel injection timing. Combustion, performance, and emissions results are presented and compared with experimental data where possible.

State-of-the-art RF front-end circuits are typically designed to operate at a single frequency. With an increasing number of available wireless standards, personal mobile communication devices require an increasing number of individually designed RF circuits. To save space and cost, one alternative possibility is to reuse much of the circuitry by utilizing electronically reconfigurable topologies. The ubiquitous low-noise amplifier is one of the many circuits that can be redesigned with the reconfigurable aspect in mind. In this thesis, previous work in reconfigurable LNAs is reviewed as well as a brief comparison of CMOS and GaAs processes used for RF amplifiers. Three new reconfigurable LNA topologies are also presented. The first two topologies, based on the common-gate stage and synchronous filters, are investigated but not manufactured. The third design, based on the cascode topology, was manufactured in a 0.5 µm GaAs process with enhancement-mode and depletion-mode pHEMTs. The LNA features 12.7 dB, 13.6 dB, and 13.9 dB of gain and noise figures of 2.7 dB, 3.5 dB, and 4.2 dB at 2.5, 3.6 and 5.8 GHz, respectively. The LNA draws 41 mA from a 3.3 V supply.

No description available.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Increasing gate counts in FPGA’s create an option of offering multiple waveform demodulation and modulation within a single transponder transceiver. Differing data rates, channel schemes, and network protocols can be addressed with the flexibility of software-based demodulation and modulation. Increased satellite longevity and reliability are benefits of software-based transceiver design. Newer packaging technology offers additional capability in reducing form factor and weight of a transponder. A review of the challenges in combining each of the above to produce the next generation of transponders is the subject of this paper.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.