<p> The realization of inductorless filters by means of RC-gyrator structures has been investigated, and the sensitivity of their response characteristics with respect to supply voltage variations has been measured. A critical appraisal is made of the various multiparameter sensitivity functions which have already been proposed in the literature, and the methods by which these sensitivity criteria may be computed are surveyed. A new index of performance, by which the multiparameter sensitivity of a linear, time-invariant network may be evaluated, is proposed. Furthermore, a new method of computing sensitivity indices is described and is shown to be highly efficient from a computational point of view. The index has been used to investigate the sensitivity performance of a wide range of passive and active filter structures. It has also been used to generate a so called "optimum tolerance set" for the elements of such filters and the effect of employing these optimum tolerance sets has been investigated.</p> <p> The index of perfonnance and the concept of the optimum tolerance set is extended to the case of RC active filters. A "two-level" optimization procedure is proposed, whereby an optimum nominal element value set may be combined with the corresponding optimum tolerance set to obtain a marked improvement in the sensitivity performance of the network. Finally, the synthesis of a highly selective RC-active filter is considered, and it is shown how an optimal structure and tolerance set can be obtained for such a network.</p> / Thesis / Doctor of Philosophy (PhD)

La dernière décennie à vu l’explosion des technologies de communication sans fils. Les normes se sont multipliées de sorte que les fonctionnalités GSM, GPS, WIFI, Bluetooth et autres cohabitent parfois au sein du même terminal. Les réseaux de capteurs (Wireless area network WSN) incluant les réseaux de capteur WPAN (Wireless Personnel Area Network) seront amenés à jouer un rôle important dans l’environnement de demain au même titre que les normes sans fils grand public que nous venons de mentionner. Le déploiement de ces capteurs à grande échelle a été rendu possible par la réduction du coût de leur fabrication via la miniaturisation des procédés de fabrication propres à la technologie CMOS. Cependant, la consommation énergétique de ces circuits doit être très réduite permettant ainsi de fonctionner dans le cas où ces mêmes capteurs sont associés à une batterie compacte embarquée de durée de vie réduite. A défaut il serait nécessaire de pouvoir se contenter de l’énergie récupérable - en quantité limité - disponible dans l'environnement direct de ces capteurs. Cette contrainte de consommation électrique réduite ainsi que la nécessité de profiter au maximum de la miniaturisation du procédé CMOS amène à considérer la conception de circuits radio sous l'angle du faible encombrement surfacique et de la consommation statique la plus faible possible. Ces contraintes sont parfois contradictoires avec les architectures classiques connues de ces circuits radio constituants les capteurs déployés.es travaux présentés dans le cadre de cette thèse s’attachent à proposer des solutions afin de répondre à ces critères de consommation et de coût. Nous nous sommes intéressés au cas des amplificateurs faible bruit (Low Noise Amplifier – LNA) et à la possibilité de réaliser ce composant critique pour le lien RF sans utiliser d’inductance intégrées tout en limitant au maximum la consommation électrique. Plusieurs solutions innovantes ont été étudiées afin de répondre à cet objectif. Ces travaux nous ont conduit à la réalisation de plusieurs prototypes de circuits en technologie CMOS 65nm et 130nm qui permettent de comprendre les limites et les avantages d’une telle approche. La première partie présentera une première approche consistant à émuler une inductance à l’aide de composants actifs et ainsi à résoudre le problème de l’encombrement propre au inductance passives. Nous verrons en quoi cette approche peut présenter des limites pratiques pour une application radio. La seconde partie présentera la réalisation d’un LNA très basse consommation et large bande qui n’utilise pas d’inductance et présentant des performances améliorées vis à vis des topologies connues de LNA à faible consommation. Nous conclurons ensuite par les perspectives ouvertes suite à ces travaux et les autres approches possibles pour répondre aux contraintes de la basse consommation et du faible coût. / During the past decade the intense development of wireless technologies standard such as WIFI, GSM or Bluetooth reshaped the connectivity environment of any technology customers Among those standards, Wireless Sensor Networks (WSN) and Wireless Personal Area Network (WPAN) are expected to play a key role in our future environments. The large scale spreading of such sensors has been enabled through the strong cost optimization of modern CMOS technologies. The autonomy improvement of such sensor is however a primary concern to allow any kind of remote operation within the limitation of battery life. Even though the emerging energy harvesting domain offer energy friendly environments for such sensor, the electrical autonomy remain as a tight challenge to address. Those requirements of autonomy along with the context of CMOS technology development pushes sometimes fundamental contradictions between circuit's miniaturization and decreased power consumption. In this work, we propose solutions to address simultaneously those autonomy-miniaturization requirements. The study presented here is focused on Low Noise Amplifiers (LNA) and more precisely on the specific case of inductorless design of LNA. Several innovative solutions has been proposed and realized in 65nm & 130nm CMOS technologies in order to highlight the pros and the cons of such design approach. First part of this work is focused on the design of an active inductance to address the area occupation of narrow band system using inductors. We'll explain why such approach rises fundamental limits for radio application. Second part details the design of an ultra low power broadband LNA without inductors. The proposed circuits enable significant improvement in performance tradeoffs for such low power consumption in comparison with known design techniques. We will conclude with general perspectives and other possible design approaches.

As is predicted by Moore’s law, the transistors in microprocessors increase dramatically. In order to increase the power density of the microprocessors, the switching frequency of the Voltage Regulator (VR) is expected to increase to MHz level. However, the frequency dependent loss will increase proportionally. In order to meet requirements of the next-generation microprocessors, three new ideas are proposed in this thesis. The first contribution is a new bipolar Current Source Driver (CSD) for high frequency power MOSFET. The proposed CSD alleviates the gate current diversion problem of the existing CSDs by clamping the gate voltage to a flexible negative value during turn off transition. Therefore, the proposed driver turns off the MOSFET much faster. For buck converters with 12 V input at 1MHz switching frequency, the proposed driver improves the efficiency from 80.5% using the existing CSD to 82.5% at 1.2V/30A, and at 1.3V/30A output, from 82.5% to 83.9%. The second contribution is an accurate analytical loss model of a power MOSFET with a CSD. The current diversion problem that commonly exists in CSDs is investigated mathematically. The inductor value of the CSD is optimized to achieve minimum loss for the synchronous buck converter. The experimentally measured loss matches the calculated loss very well. The efficiency with the optimal CSD inductor is improved from 86.1% to 87.6% at 12V input, 1.3V/20A output in 1MHz switching frequency and from 82.4% to 84.0% at 1.3V/30A output. The third contribution is a new inductorless bipolar gate driver for control FET of buck converters. The most important advantage of the driver presented in this thesis is that it can turn off the power MOSFETs with a negative voltage, which will significantly reduce the turn off time and thus switching loss. In addition, the proposed bipolar gate driver has no inductor in the driver circuit; therefore it can be fully integrated into a chip. For buck converter with 5V input, 1.3V/25A load, in 2 MHz frequency, the proposed gate driver increases the efficiency from 75.8% to 77.8% and from 72.9% to 76.5% at 5V input, 1.3V/25A load, in 2.5 MHz switching frequency. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-07-30 14:06:04.003

A brief analysis of the nonresonant-coupled parallel resonant converter is performed. The converter is modeled and a reference classical analog controller is designed and simulated. Infrastructure required for digital control of the converter (including anti-aliasing filters and a modulator) is designed and a classical digital controller is designed and simulated, yielding a ~30% degradation in control bandwidth at the worst-case operating point as compared with the analog controller. Based on the strong relationship observed between low-frequency converter gain and operating point, a gain-scheduled digital controller is proposed, designed, and simulated, showing 4:1 improved worst-case control bandwidth as compared with the analog controller. A complete prototype is designed and built which experimentally validates the results of the gain-scheduled controller simulation with good correlation. The three approaches that were investigated are compared and conclusions are drawn. Suggestions for further research are presented. / Master of Science

Le secteur des communications sans fil a connu un essor considérable, soutenu par l’évolution des "smartphones" et par le développement des réseaux de capteurs sans fil et de l’Internet des Objets (connu en anglais sous le nom ‘IoT’ pour Internet of Things). Les applications actuelles visent l’autonomie énergétique des objets communicants et nécessitent la conception de circuits intégrés pouvant assurer à la fois un fonctionnement à hautes performances et à moindre coût. L’une des principales fonctions des systèmes de communications radiofréquences (RF) est la génération de fréquence, assurée par l’oscillateur. De nombreux efforts de conception sont ainsi nécessaires afin d’assurer les performances requises par les nouvelles applications sans fil. Nos travaux de recherche ont pour objectif de proposer une méthode de conception d’oscillateurs agiles à faible consommation au sein des systèmes d’émission-réception RF. Le travail s’est focalisé sur l’étude et l’optimisation des éléments constitutifs d’un oscillateur LC passif en technologie CMOS et sur la proposition d’une méthode de conception. La méthode proposée peut être exploitée pour différentes structures d’oscillateurs afin d’optimiser leurs performances essentiellement en termes de consommation de puissance et de bruit de phase. Cette méthode a été appliquée pour implémenter plusieurs VCOs en technologie CMOS. Une série de mesure sous pointes a permis de valider leur fonctionnement. La suite de ce travail de thèse est consacrée à la proposition d’une nouvelle topologie d’oscillateur LC reconfigurable à base d’inductance active dédiée aux applications multistandards faible coût / The rapid growth of the Internet of Things (IoT) applications and the wireless sensor networks boosts the need for low cost and low power radiofrequency (RF) transceivers. The voltage-controlled oscillator (VCO) is an essential building block of several RF transceivers. Design tradeoffs have been very stringent in terms of power consumption, phase-noise, area and tuning range. In this context, the aim of this work is to propose a design method, aiming to optimize the VCO design and to improve its performances essentially in terms of power consumption and phase noise.The first part of this thesis sets a study of the elements of passive LC oscillators in CMOS technology. The second part presents a complete design method, aiming to optimize the LC-VCO performance regarding the phase noise and power consumption. The evaluation of the proposed method is carried out with some test-cases in full CMOS technology. Many RF LC-VCOs have been implemented and measured. The final part of this thesis presents a new tunable VCO suitable for multi-standards applications. The frequency tuning of the VCO is ensured using an active inductor based on CMOS inverters. The desired bandwidth can be selected while achieving low surface area and low power consumption.

Ultra low power wireless sensors and sensor systems are of increasing interest in a variety of applications ranging from structural health monitoring to industrial process control. Electrochemical batteries have thus far remained the primary energy sources for such systems despite the finite associated lifetimes imposed due to limitations associated with energy density. However, certain applications (such as implantable biomedical electronic devices and tire pressure sensors) require the operation of sensors and sensor systems over significant periods of time, where battery usage may be impractical and add cost due to the requirement for periodic re-charging and/or replacement. In order to address this challenge and extend the operational lifetime of wireless sensors, there has been an emerging research interest on harvesting ambient vibration energy. Vibration energy harvesting is a technology that generates electrical energy from ambient kinetic energy. Despite numerous research publications in this field over the past decade, low power density and variable ambient conditions remain as the key limitations of vibration energy harvesting. In terms of the piezoelectric transducers, the open-circuit voltage is usually low, which limits its power while extracted by a full-bridge rectifier. In terms of the interface circuits, most reported circuits are limited by the power efficiency, suitability to real-world vibration conditions and system volume due to large off-chip components required. The research reported in this thesis is focused on increasing power output of piezoelectric transducers and power extraction efficiency of interface circuits. There are five main chapters describing two new design topologies of piezoelectric transducers and three novel active interface circuits implemented with CMOS technology. In order to improve the power output of a piezoelectric transducer, a series connection configuration scheme is proposed, which splits the electrode of a harvester into multiple equal regions connected in series to inherently increase the open-circuit voltage generated by the harvester. This topology passively increases the rectified power while using a full-bridge rectifier. While most of piezoelectric transducers are designed with piezoelectric layers fully covered by electrodes, this thesis proposes a new electrode design topology, which maximizes the raw AC output power of a piezoelectric harvester by finding an optimal electrode coverage. In order to extract power from a piezoelectric harvester, three active interface circuits are proposed in this thesis. The first one improves the conventional SSHI (synchronized switch harvesting on inductor) by employing a startup circuitry to enable the system to start operating under much lower vibration excitation levels. The second one dynamically configures the connection of the two regions of a piezoelectric transducer to increase the operational range and output power under a variety of excitation levels. The third one is a novel SSH architecture which employs capacitors instead of inductors to perform synchronous voltage flip. This new architecture is named as SSHC (synchronized switch harvesting on capacitors) to distinguish from SSHI rectifiers and indicate its inductorless architecture.

Les systèmes de communication mobiles permettent l’utilisation de l’information en environnements complexes grâce à des dispositifs portables qui ont comme principale restriction la durée de leurs batteries. Des nombreux efforts se sont focalisés sur la réduction de la consommation d’énergie des circuits électroniques de ces systèmes, une fois que le développent des technologies des batteries ne avance pas au rythme nécessaire. En outre, les systèmes RF sont généralement conçus pour fonctionner de manière fixe, spécifiés pour le pire cas du lien de communication. Toutefois, ce scénario peut se produire dans une petite partie du temps, entraînant ainsi en perte d’énergie dans le reste du temps. La recherche des circuits RF adaptatifs, pour adapter le niveau du signal d'entrée pour réduire la consommation d'énergie est donc d'un grand intérêt et de l'importance. Dans la chaîne de réception radiofréquence, l'amplificateur à faible bruit (LNA) se montre un composant essentiel, autant pour les performances de la chaîne que pour la consommation d'énergie. Au cours des dernières décennies, des techniques pour la conception de LNAs reconfigurables ont été proposées et mises en oeuvre. Cependant, la plupart d'entre elles s’applique seulement au contrôle du gain, sans exploiter Le réglage de la linéarité et du bruit envisageant l'économie d'énergie. De plus,ces circuits occupent une grande surface de silicium, ce qui entraîne un coût élevé, ou NE correspondent pas aux nouvelles technologies CMOS à faible coût. L'objectif de cette étude est de démontrer la faisabilité et les avantages de l'utilisation d'un LNA reconfigurable numériquement dans une chaîne de réception radiofréquence, du point de vue de la consommation d'énergie et de coût de fabrication. / Mobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power. / Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência.