New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored.

Reliable access to power is essential for modern society’s fundamental functions. It is necessary that faults and abnormalities in low-voltage grids can easily be detected and diagnosed. A fault in a grid can be a consequence of several causes, including internal damage, technical errors, malfunctioning electricity meters and electricity theft. This thesis investigates the possibilities with model-based approaches for fault diagnosis and monitoring of low-voltage grids. Data and properties from a real low-voltage grid is utilised in this thesis. Furthermore, hypothetical sensors are introduced in the model equations and simulations. To delimit and make the results easier to understand, three different clusters, made up from a few households and intermediate cables, from the grid are analysed. The methods used includes modelling of the real low-voltage grid, structural analysis of the isolability performance of faults, and simulation of faulty scenarios in MATLAB. The investigation of the isolability performance uses isolability matrices and Dulmage Mendelsohn decomposition. The results from the structural analysis show that it is hard to design residuals that are only sensible to certain faults and draw conclusions on where a particular fault takes place. Many times, it shows that several faults cannot be isolable from each other. The redundancy has to be increased in the equations with even more sensors. By using the simulated model directly for residual generation, clearer and more determined results can be seen. Because it does take quantities into account, it is easier to analyse and look after changes in the grid. A few introduced sensors can often tell where a current through a cable must have been increased. An injected fault will more or less always affect residuals indirect proximity. However, because faults can occur in both sensors and cables, itis often hard to specify exactly why and where the fault takes place.

In this diploma thesis there is elaborated design of low-voltage power supply block using I3T25 technology. The theoretical part describes the basic structures used in the design, using CMOS and bipolar devices. Furthermore, the properties and the analysis used in the evaluation are described. In the design part there is an elaborated design of individual parts, including voltage references, current references, DAC converter, operational amplifier. In the last part, the power supply block is subjected to simulations for verification of temperature compensated output variables and analyzed circuit functionality.

The work deals with the analog design of low-voltage and low-power differential difference amplifier DDA with adaptive differential input stage, second stage class AB, improved by a self – cascode to achieve higher gain and slew rate. Conventional and unconventional techniques, and methods for low-voltage and low-power design are presented. The finished design of the differential difference amplifier DDA with the analyzed results is presented. Design of a Butterwortho low-pass filter of the sixth order based on DDA with Sallen Key topology and design of a multifunctional ARC filter based on DDA.

The following technical report describes the development and testing of an arc fault circuit interrupter (AFCI) for DC circuits operating primarily at 48 volts. We have identified an effective method for determining when arcing is occurring. Our method is primarily based on comparing the frequency spectrum of current flowing through the circuit during an arcing event to a known characteristic spectrum. Once an arc has been identified, our interrupter is capable of responding adequately to eliminate the arc. Hardware tests show the AFCI developed in this thesis responded, in all test cases, within 2 seconds of an arc fault occurrence. Commercialization and adoption of our interrupter will increase the safety of DC circuits operating at 80 volts or less.

This thesis focuses on design of an accurate digital to analog converter (DAC). The thesis provides material to understand the principle of conversion of digital signal to analog signal. Some possible structures of DAC are described in this thesis. The selected structure is used for design of the DAC using the CMOS 07 technology. Functionality of the DAC is verified with simulations using the PSPICE simulation program.

This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don't require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limited. This creates strong demand for low power, lower voltage circuits. The RF and analog circuits in the wireless sensor usually consume most of the power. This motivates the research presented in the dissertation. Specially, the research focuses on the design of a low power high efficiency regulator, low power Resistance to Digital Converter (RDC), low power Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with parasitic error reduction and a low power low voltage Low Dropout (LDO) regulator. This dissertation includes a low power analog circuit design for the RFID wireless sensor which consists of the energy harvest circuits (an optimized rectifier and a regulator with high current efficiency) and a sensor measurement circuit (RDC), a single end sampling SAR ADC with no error induced by the parasitic capacitance and a digital loop LDO whose line and load variation response is improved. These techniques will boost the design of the wireless sensor and they can also be used in other similar low power design.

In last decade, there is a large increase in installed capacity of wind power. Asmore wind power is integrated into utility networks, related technologychallenges draw much attention. The doubly fed induction generator (DFIG) isthe mainstream choice for wind turbine generator (WTG) in current market andthe object of this thesis. It is very sensitive to voltage dips. The enhancement oflow voltage ride through (LVRT) is one of the most important issues for DFIG,and many works have already been done to provide solutions.In current works, the voltage dip waveforms that are applied in LVRTrelated works are largely different from waveforms in reality, because they failto consider the the effect of realistic wind farm configurations on waveforms ofvoltage dips and significant influences of additional characteristics of voltagedips. The true impact of the voltage dip needs to be assessed in performanceevaluation and development of LVRT methods. To support the development ofpractical LVRT capacity enhancement solutions, the application of voltage dipknowledge is definitely demanded.In this thesis, the characteristics of realistic waveform voltage dips in windfarm are analyized based on voltage dip knowldege from power quality field,measured voltage dip from industry and realistic wind farm configurations.Classical analysis theory is applied to explain the principles of the impact ofvoltage dip characteristics on dynamic behavior of DFIG. The impacts of manywidely neglected characteristics such as phase angle jump (PAJ), point on wave(POW) of initiation and recovery, voltage recovery process, transformerconfigurations, load effect are revealed and verified by simulations. The impactof many voltage dip characteristics on DFIG are studied for the first time. / De senaste tio åren har sett en stor ökning av installerad effekt av vindkraft.Mer vindkraft i elnäten har lett till större uppmärksamhet om dess tekniskautmaningar. Den dubbelmatad asynkrongenerator (DFIG) är idag denvanligaste förekommande typen i vindkraftverk. Den är mycket känslig förspänningssänkningar. Förbättring av tålighet för spänningssänkningar (LVRT)är en av de viktigaste frågorna för DFIG, och många studier har redan söktlösningar.I befintliga studier om LVRT har spänningssänkningarna skiljt sig väsentligtfrån verkliga vågformer, då de inte har tagit hänsyn till realistiskavindparkkonfigurationer och betydande påverkan av ytterligare egenskaper hosspänningssänkningar. För att stödja utvecklingen av praktiska LVRT lösningarbehövs mer kunskap om spänningssänkningar för att bedöma dess verkligainverkan.Detta examensarbete förbättrar LVRT analysen av DFIG genom att tillämpakunskap om spänningssänkningar från elkvalitetsområdet, tillsammans medrealistiska vindparkskonfigurationer. Inflytandet av ändringar i fasvinkel(PAJ), fasvinkeln vid sänkning och återhämtning (POW), spänningsåterhämtning, transformatorkonfigurationer, last och många andra egenskaperav spänningssänkningar ingår också. Inflytandet av många egenskaper avspänningssänkningar studeras här akademiskt för första gången. Denkaraktäristik av realistiska spänningssänkningar som inträffar vid generatornspoler, och de effekter dessa har, studeras och förklaras genom teoretisk analysoch intensiva simuleringar.

This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage amplifier with a bulk-driven input pair while showing no bandwidth degradation when compared to amplifier architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0.35um dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail differential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT+2Vds,sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-differential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds,sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the efficacy of the design architectures and techniques presented in this dissertation.

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of lowvoltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in iv characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysiliconbound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode’s design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode’s overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes v increasingly important in today’s manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices’ dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on vi uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers.