Gegenstand dieser Dissertation ist die Rolle fiskalischen Stresses auf die Größe des Staatsausgabenmultiplikators. Hierbei werden zuerst die Folgen von empirisch identifizierten Staatsausgabenschocks in Italien untersucht. Dies geschieht sowohl in einem Zustand mit hohen Risikospreads auf Staatsanleihen, als auch in einem Zustand mit niedrigen Risikospreads. Das Resultat ist, dass kumulative Multiplikatoren kleiner sind, wenn das Ausfallrisiko von Staatsanleihen hoch ist. Zweitens erklärt die Dissertation dieses empirische Resultat im Rahmen eines DSGE Models. Im Model verdrängt ein Anstieg der Staatsausgaben private Investitionen. Der Verdrängungseffekt wird durch fragile Banken und die Rolle aggregierten Risikos ausreichend verstärkt, so dass fiskalischer Stress zu sehr kleinen oder sogar negativen Multiplikatoren führen kann. Zuletzt untersuche ich die Rolle fiskalischen Stresses auf den Staatsausgabenmultiplikator unter der Nebenbedingung, dass die nominale Zinsuntergrenze bei null bindet. In diesem Szenario kann sich der Effekt fiskalischen Stresses ins Gegenteil verkehren und der Staatsausgabenmultiplikator groß werden. / This thesis examines the role of fiscal stress on the size of the government spending multiplier. First, it explores the dynamic consequences of empirically identified government spending shocks in Italy in a regime with high sovereign bond yield spreads and a regime with low spreads. It finds that cumulative multipliers are lower when sovereign risk spreads are high. Secondly, the thesis explains the empirical result of small government spending multipliers in times of high levels of fiscal stress in the context of a DSGE Model. In this model, an increase in government spending crowds out private investment. A fragile banking sector and aggregate risk amplify the crowding out of investment sufficiently to imply small multipliers in the presence of fiscal stress. Finally, I analyze the role of fiscal stress on the multiplier, when the economy is at the zero lower bound for nominal interest rates and find that in this scenario, the effect of fiscal stress is reversed and the government spending multiplier is large.

Diese Arbeit befasst sich mit einem Multiplier-Bootstrap Verfahren für die Konstruktion von Likelihood-basierten Konfidenzbereichen in zwei verschiedenen Fällen. Im ersten Fall betrachten wir das Verfahren für ein einzelnes parametrisches Modell und im zweiten Fall erweitern wir die Methode, um Konfidenzbereiche für eine ganze Familie von parametrischen Modellen simultan zu schätzen. Theoretische Resultate zeigen die Validität der Bootstrap-Prozedur für eine potenziell begrenzte Anzahl an Beobachtungen, eine große Anzahl an betrachteten parametrischen Modellen, wachsende Parameterdimensionen und eine mögliche Misspezifizierung der parametrischen Annahmen. Im Falle eines einzelnen parametrischen Modells funktioniert die Bootstrap-Approximation, wenn die dritte Potenz der Parameterdimension ist kleiner als die Anzahl an Beobachtungen. Das Hauptresultat über die Validität des Bootstrap gilt unter der sogenannten Small-Modeling-Bias Bedingung auch im Falle, dass das parametrische Modell misspezifiert ist. Wenn das wahre Modell signifikant von der betrachteten parametrischen Familie abweicht, ist das Bootstrap Verfahren weiterhin anwendbar, aber es führt zu etwas konservativeren Schätzungen: die Konfidenzbereiche werden durch den Modellfehler vergrößert. Für die Konstruktion von simultanen Konfidenzbereichen entwickeln wir ein Multiplier-Bootstrap Verfahren um die Quantile der gemeinsamen Verteilung der Likelihood-Quotienten zu schätzen und eine Multiplizitätskorrektur der Konfidenzlevels vorzunehmen. Theoretische Ergebnisse zeigen die Validität des Verfahrens; die resultierende Approximationsfehler hängt von der Anzahl an betrachteten parametrischen Modellen logarithmisch. Hier betrachten wir auch wieder den Fall, dass die parametrischen Modelle misspezifiziert sind. Wenn die Misspezifikation signifikant ist, werden Bootstrap-generierten kritischen Werte größer als die wahren Werte sein und die Bootstrap-Konfidenzmengen sind konservativ. / The thesis studies a multiplier bootstrap procedure for construction of likelihood-based confidence sets in two cases. The first one focuses on a single parametric model, while the second case extends the construction to simultaneous confidence estimation for a collection of parametric models. Theoretical results justify the validity of the bootstrap procedure for a limited sample size, a large number of considered parametric models, growing parameters’ dimensions, and possible misspecification of the parametric assumptions. In the case of one parametric model the bootstrap approximation works if the cube of the parametric dimension is smaller than the sample size. The main result about bootstrap validity continues to apply even if the underlying parametric model is misspecified under a so-called small modelling bias condition. If the true model deviates significantly from the considered parametric family, the bootstrap procedure is still applicable but it becomes conservative: the size of the constructed confidence sets is increased by the modelling bias. For the problem of construction of simultaneous confidence sets we suggest a multiplier bootstrap procedure for estimating a joint distribution of the likelihood ratio statistics, and for adjustment of the confidence level for multiplicity. Theoretical results state the bootstrap validity; a number of parametric models enters a resulting approximation error logarithmically. Here we also consider the case when parametric models are misspecified. If the misspecification is significant, then the bootstrap critical values exceed the true ones and the bootstrap confidence set becomes conservative. The theoretical approach includes non-asymptotic square-root Wilks theorem, Gaussian approximation of Euclidean norm of a sum of independent vectors, comparison and anti-concentration bounds for Euclidean norm of Gaussian vectors. Numerical experiments for misspecified regression models nicely confirm our theoretical results.

The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in the early 90s as an alternative to the Schottky barrier diode (SBD) technology for microwave detector applications due to its highly stable temperature characteristics. The ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a thin barrier, which enables RF detection at zero bias from microwaves up to submillimetre wave frequencies. In this work, two heavily doped GaAs contact layer on top and bottom layers adjacent to lightly doped GaAs intermediate layers, enclose undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that acts as a tunnel barrier. The ultimate ambition of this work was to develop a MMIC detector as well as a frequency source based on optimized ASPAT diodes for millimetre wave (100GHz) applications. The effect of material parameter and dimensions on the ASPAT source performances was described using an empirical model for the first time. Since this is a new device, keys challenges in this work were to improve DC and RF characteristic as well as to develop a repeatable, reproducible, and ultimately manufacturable fabrication process flow. This was investigated using two approaches namely air-bridge and dielectric-bridge fabrication process flows. Through this work, it was found that the GaAs/AlAs heterostructures ASPAT diode are more amenable to the dielectric-bridge technique as large-scale fabrication of mesa area up to 4×4Âμm2 with device yields exceeding 80% routinely produced. The fabrication of the ASPAT using i-line optical lithography which has the capability to reduce emitter area to 4×4Âμm2 to lower down the device capacitance for millimetre wave application has been made feasible in this work. The former challenge was extensively studied through materials and structural characterisations by a SILVACO physical modelling and confirmed by comparison with experimental data. The I-V characteristic of the fabricated ASPAT demonstrated outstanding scalability, demonstrating robust processing. A fair comparison has been made between ASPAT and SBD fabricated in-house; indicating ASPAT is extremely stable to the temperature. The RF characterisations were carried out with the aid of Keysight ADS software. The DC characteristic from fabricated GaAs/AlAs ASPAT diodes were absorbed into an ADS simulation tool and utilized to demonstrate the performance of MMIC 100GHz detector as well as 20GHz/40GHz signal generators. Zero bias ASPAT with mesa area of 4×4Âμm2 with video resistance of 90KΩ, junction capacitance of 23fF and curvature coefficient of 23V-1 has demonstrated detector voltage sensitivity above 2000V/W, while the signal source conversion loss and conversion efficiency are 28dB and 0.3% respectively. An estimate noise equivalent power (NEP) for this particular device is 18.8pW/Hz1/2.

Submitted by Maicon Juliano Schmidt (maicons) on 2015-05-05T13:21:40Z No. of bitstreams: 1 Marília Rodrigues.pdf: 4635899 bytes, checksum: e6ae4c9abe358047ed6135bcdbcb3480 (MD5) / Made available in DSpace on 2015-05-05T13:21:40Z (GMT). No. of bitstreams: 1 Marília Rodrigues.pdf: 4635899 bytes, checksum: e6ae4c9abe358047ed6135bcdbcb3480 (MD5) Previous issue date: 2014-02-27 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / UNISINOS - Universidade do Vale do Rio dos Sinos / A dificuldade para visualizar o retorno que os investimentos na área social podem gerar para a sociedade e para a economia do país faz com que, tanto as empresas como o governo, não tenham a real dimensão das consequências destes investimentos ao longo do tempo. Dentro deste contexto, a presente pesquisa teve como objetivo desenvolver um modelo computacional do Balanço Social Sistêmico Dinâmico, a fim de visualizar o efeito multiplicador gerado pelos investimentos do governo brasileiro na área social. O método de pesquisa adotado foi a Design Science Research que caracteriza-se pela construção e avaliação de artefatos desenvolvidos com o propósito de solucionar um problema. Na primeira fase da pesquisa, definiu-se a problemática envolvida neste estudo e elaborou-se o referencial teórico, onde os principais temas para o desenvolvimento da pesquisa foram abordados. Na segunda, selecionou-se as variáveis que foram utilizadas para a construção de uma estrutura sistêmica. Nesta fase também desenvolveu-se um modelo computacional piloto e o modelo computacional do Balanço Social Sistêmico Dinâmico. Na terceira e última fase, criou-se e simulou-se alguns cenários. Os resultados gerados pelos cenários foram utilizados para o cálculo do efeito multiplicador, que leva em consideração a evolução do PIB e dos gastos com saúde e educação. A partir do cálculo do efeito multiplicador concluiu-se que investimentos governamentais na área social geram impactos positivos sobre a economia do país. Onde o investimento em educação foi o que apresentou maior impacto sobre o PIB. No entanto, deve-se fazer uma combinação entre os investimentos em saúde, educação e infraestrutura tendo em vista a interdependência dos investimentos. / The difficulty to visualize the return that the investment in the social area can generate for society and the country economy, consequently makes both companies and the government, do not have the actual magnitude of the consequences of these investments over time. Within this context, the present research aimed to develop a computational model of a Systemic Dynamic Social Balance to view the multiplier effect generated by the investments of the Brazilian government in the social area. The research method adopted was the Design Science Research that is characterized by the construction and evaluation of artifacts developed for the purpose of to solve a problem. In the first phase of the research, was defined the problems involved in this study and drafted up the theoretical framework where the main themes for the development of the research were discussed. In the second, was selected the variables that were used to construct a systemic framework. At this stage was also developed a computational model pilot and computational model of a Systemic Dynamic Social Balance. In the third and final phase was created and simulated up some scenarios. The results generated by the scenarios were used to calculate the multiplier effect, which considers the evolution of GDP and costs on health and education. Whereof the calculation of the multiplier effect it was concluded that governmental social investments generate positive impacts on the economy of the country. Investment in education showed the greatest impact on GDP. However, one must make a combination between investments in health, education and infrastructure in view of the interdependence between investments.

本文利用Hendry's ECM Methodology的內容，建立台灣貨幣需求模形，並計算其彈性以與國內相關貨幣需求文獻比較。

<p>Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.</p><p>In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.</p><p>In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.</p><p>The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.</p><p>Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.</p>

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well. In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources. In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations. The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs. Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

Obiettivo di questo lavoro è studiare i fattori socio-economici responsabili del cambiamento nella distribuzione del reddito dovuto a un cambiamento nel contesto politico di riferimento, in Vietnam durante il periodo delle riforme. La metodologia adottata analizza i cambiamenti nella distribuzione del reddito sia a livello micro che a livello macro. A livello micro, l'analisi indaga sulle caratteristiche individuali e familiari da cui dipende il livello e la distribuzione della spesa. E' possibile inoltre valutare gli effetti diretti di cambiamenti nel quadro politico di riferimento. Il livello macro di analisi consente di individuare le caratteristiche strutturali della disuguaglianza nella distribuzione del reddito personale e di isolare anche gli effetti indiretti delle politiche. Gli strumenti analitici selezionati in questo studio sono un modello supply-driven, rappresentato da un modello di microsimulazione e un modello demand-driven, costituito dalla Matrice di Contabilità Sociale. In particolare, il modello di microsimulazione ha consentito la derivazione di una distribuzione controfattuale e la disaggregazione della variazione della disuguaglianza in Vietnam in: effetto di prezzo, effetto di una variazione della componente non osservata dei salari, effetto dovuto a cambiamenti nelle scelte occupazioni e effetti dovuti a cambiamenti nella popolazione. Utilizzando una nuova metodologia di scomposizione ad un livello microscopico dei moltiplicatori derivati dalla SAM, è stato possibile derivare e isolare tutti gli effetti diretti e indiretti di uno shock esogeno sulla distribuzione personale del reddito. / The aim of this work is to investigate the socio-economic factors that affect in income distribution changes caused by changes in the policy framework in Vietnam during the period of reforms. The adopted methodology analyzes policy induced changes in income distribution both at the micro and the macro level. At the micro level, the analysis of inequality can help identifying the socio-economic factors affecting the level of household expenditure and its distribution and evaluating direct effects of policies. The macro level identifies the structural characteristics of inequality and evaluates also the indirect effects of policies on the personal income distribution. The two analytical tools have been selected have been a supply driven model represented by the microsimulation model and a demand driven model, constituted by the Social Accounting Matrix. The microsimulation model allowed deriving a counterfactual distribution of income and disaggregating change in the Vietnamese income inequality into four effects: price effect, effect of a change in the unobservable component of wages, occupational choice effect and population effect. Using a new technique of decomposition of SAM-based multipliers in 'microscopic' detail, the macro model allowed deriving all the direct and indirect effects of an exogenous shock to personal income distribution.

Cryptography algorithms like the Advanced Encryption Standard, Elliptic Curve Cryptography algorithms etc are designed using algebraic properties of finite fields. Thus performance of these algorithms depend on performance of the underneath field operations. Moreover, different algorithms use finite fields of widely varying order. In order to cater to these finite fields of different orders in an area efficient manner, it is necessary to design solutions in the form of hardware-consolidations, keeping the performance requirements in mind. Due to their small area occupancy and high utilization, such circuits are less likely to stay idle and therefore are less prone to loss of energy due to leakage power dissipation. There is another class of applications that rely on finite field algebra namely the various error detection and correction techniques. Most of the classical block codes used for detection of bit-error in communications over noisy communication channels apply the algebraic properties of finite fields. Cyclic redundancy check is one such algorithm used for detection of error in data in computer network. Reed-Solomon code is most notable among classical block codes because of its widespread use in storage devices like CD, DVD, HDD etc. In this work we present the architecture of a polymorphic multiplier for operations over various extensions of GF(2). We evolved the architecture of a textbook shift-and-add multiplier to arrive at the architecture of the polymorphic multiplier through a generalized mathematical formulation. The polymorphic multiplier is capable of morphing itself in runtime to create data-paths for multiplications of various orders. In order to optimally exploit the resources, we also introduced the capability of sub-word parallel execution in the polymorphic multiplier. The synthesis results of an instance of such a polymorphic multipliershowsabout41% savings in area with 21% degradation in maximum operating frequency compared to a collection of dedicated multipliers with equivalent functionality. We introduced the multiplier as an accelerator unit for field operations in the coarse grained runtime reconfigurable platform called REDEFINE. We observed about 40-50% improvement in performance of the AES algorithm and about 52×improvement in performance of Karatsuba-Ofman multiplication algorithm.

This thesis reports the work done towards design and fabrication of a versatile and low cost, frequency domain DOT (Diffuse Optical Tomography) Imager. A design which uses only a single fiber for the source and a single fiber bundle for the detector is reported. From near the source, to diametrically opposite to the source, the detected intensity of scattered light varies by three to four orders in magnitude, depending on the tissue/phantom absorption and scattering properties. The photo multiplier tube’s (PMT’s) gain is controlled to operate it in the linear range, thus increasing the dynamic range of detection. Increasing the dynamic range by multi channel data acquisition is also presented. Arresting the oscillations of a stepper using a negative torque braking method is also adopted in this application for increasing the speed of data acquisition. The finite element method (FEM) for obtaining photon density solution to the transport equation and the model based iterative image reconstruction (MPBIIR) algorithm are developed for verifying the experimental prototype. Simulation studies presented towards the end of this thesis work provide insight into the nature of measurements. The optical absorption reconstructed images from the simulation, verified the validity of implementation of the reconstruction method for further reconstructions from data gathered from the developed imager. A single iteration of MOBIIR to segment the region of interest (ROI) using an homogeneous measurement estimate is presented. Using the single iteration MOBIIR to obtain a relatively more accurate starting value for the optical absorption coefficient, and the reconstruction results for data obtained from tissue mimicking solid epoxy-resin phantom with a single in-homogeneity inclusion is also presented to demonstrate the imager prototype.