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Board level energy comparison and interconnect reliability modeling under drop impactAgrawal, Akash. January 2009 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.
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Modeling of power supply noise in large chips using the finite difference time domain methodChoi, Jinseong 12 1900 (has links)
No description available.
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Synthesis of tin, silver and their alloy nanoparticles for lead-free interconnect applicationsJiang, Hongjin 26 March 2008 (has links)
This thesis is devoted to the research and development of low processing temperature lead-free interconnect materials for microelectronic packaging applications with an emphasis on fundamental studies of nanoparticles synthesis, dispersion and oxidation prevention, and nanocomposites fabrication.
Oxide-free tin (Sn), tin/silver (96.5Sn3.5Ag) and tin/silver/copper (96.5Sn3.0Ag0.5Cu) alloy nanoparticles with different sizes were synthesized by a low temperature chemical reduction method. Both size dependent melting point and latent heat of fusion of the synthesized nanoparticles were obtained. The nano lead-free solder pastes/composites created by dispersing the SnAg or SnAgCu alloy nanoparticles into an acidic type flux spread and wet on the cleaned copper surface at 220 to 230 ¡æ. This study demonstrated the feasibility of nano sized SnAg or SnAgCu alloy particle pastes for low processing temperature lead-free interconnect applications in microelectronic packaging.
Surface functionalized silver nanoparticles and silver fakes were used as fillers for electrically conductive adhesives (ECAs) applications. During the curing of epoxy resin (150 ¡æ), the surfactants were debonded from the particles and at the same time the oxide layers on the particle surfaces were removed which facilitated the sintering of Ag nanoparticles. The contact interfaces between fillers were significantly reduced and an ultra highly conductive ECA with a resistivity of 5 ¡Á 10-6 ohm.cm was obtained.
To enhance the adhesion of carbon nanotube (CNT) films to substrates, an ultra highly conductive ECA were used as a media to transfer the CNT films to copper substrates. The polymer wetted along the CNTs during curing process by the capillary force. An ohmic contact was formed between the copper substrates and the transferred CNTs. This process could overcome the serious obstacles of integration of CNTs into integrated circuits and microelectronic device packages by offering low processing temperatures and improved adhesion of CNTs to substrates. The transferred CNTs can be used to simultaneously form electrical and mechanical connections between chips and substrates.
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Design and fabrication of free-standing structures as off-chip interconnects for microsystems packagingKacker, Karan 08 August 2008 (has links)
It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.
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Process development and reliability study for 01005 components in a lead-free assembly environmentBhalerao, Vikram. January 2008 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008. / Includes bibliographical references.
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Evaluation of secondary wire bond integrity on silver plated and nickel/palladium based lead frame plating finishesSrinivasan, Guruprasad. January 2008 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008. / Includes bibliographical references.
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Rework & reliability of area array componentsMajeed, Sulman. January 2009 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engfineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.
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Etude prospective de la topologie MMC et du packaging 3D pour la réalisation d’un variateur de vitesse en moyenne tension / Prospective study on medium-voltage drive with MMC Topology and 3D packaging power modulesWu, Cong Martin 08 April 2015 (has links)
La topologie modulaire multiniveaux est une structure d'électronique de puissance construite par la mise en série de sous-modules identiques, composés chacun d'une cellule de commutation et d'un condensateur. Un tel système de conversion pouvant comporter un grand nombre de cellules permet d'augmenter le rendement global et la qualité des signaux en sortie. De plus, il permet d'utiliser des composants basse tension présentant un meilleur comportement dynamique et un rapport qualité-prix bien supérieur aux composants moyenne tension. Il permet également, par rapport aux structures conventionnelles, une grande souplesse pour la conception et la fabrication du fait de son aspect modulaire, tout en s'affranchissant d'un transformateur volumineux et onéreux en entrée. Comparé aux autres types de topologies, avantageuses avec un nombre limité de niveaux, le convertisseur modulaire multiniveaux semble être mieux adapté aux applications en moyenne et haute tensions, qui sont tributaires de l'association des composants de puissance. Néanmoins, pour la variation de vitesse, un certain nombre de défis technologiques ont été mis en évidence, compte tenu du fonctionnement particulier de l'onduleur modulaire multiniveaux et des contraintes imposées par l'opération en très basse fréquence. En le fonctionnement normal, la forme d'onde des courants internes, contrairement aux autres types de topologies, n'est pas symétrique en raison de la distribution du courant direct dans chaque bras. Cela entraîne une disparité significative en termes de dissipation thermique parmi les interrupteurs constituant un sous-module. Avec le choix d'une technologie de packaging 3D, la possibilité de refroidir les puces semi-conductrices en double-face offre une meilleure capacité de refroidissement et une nouvelle perspective de conception des modules pour cette application. Un nouveau concept de report de puces est présenté et un prototype de tel module a été réalisé, modélisé et caractérisé. Il permet d'équilibrer globalement la chaleur dissipée par les puces sur les deux faces du module, problème inhérent à l'emploi de structure 3D. Conjugué à la mutualisation d'un interrupteur par deux puces en parallèle, la nouvelle architecture a aussi pour objectif d'équilibrer le refroidissement double-face dans le temps. En effet, pour les opérations en basse fréquence, les interrupteurs fonctionnent en régime instationnaire avec de forte variation de température, il n'est donc plus possible de compenser les effets thermomécaniques de chaque composant l'un par l'autre, comme en régime stationnaire et avec un positionnement planaire des puces. D'autre part, d'un point de vu systémique, la stratégie de commande et le dimensionnement des condensateurs flottants de l'onduleur modulaire multiniveaux sont deux aspects intimement liés. En effet, les condensateurs flottants sont le siège d'ondulations de tension de très forte amplitude. Cela a pour effet de déstabiliser l'onduleur, voire de provoquer la destruction des composants en atteignant des niveaux de tension trop élevés. Ainsi, des contrôleurs judicieusement conçus permettent de réduire les ondulations indésirables, et a fortiori, d'embarquer des capacités moins importantes dans le système, tant que ces dernières sont inversement proportionnelles à l'ondulation de la tension. Afin d'avoir une compréhension approfondie sur les dynamiques régissant le convertisseur modulaire multiniveaux, un modèle dynamique global basé sur la représentation d'état a été établi. Bien que cette représentation soit limitée à l'harmonique 2 des grandeurs caractéristiques, elle permet une fidèle interprétation du mécanisme de conversion sans passer par des modèles énergétiques bien plus complexes à exploiter, et de proposer des lois de commande montrant leur efficacité notamment autour de la fréquence nominale. Cela a été vérifié sur une maquette de puissance réalisée dans le cadre de cette thèse. / Multilevel modular topology converts energy between two direct and alternative endings. This structure is constructed by the series connection of identical sub-modules, composed of a switching cell and a floating capacitor, and with arm inductors. Such a conversion system may reach a large number of levels increases the overall efficiency and quality of the output signals. In addition, it allows the use of low voltage components with better dynamics and cost effectiveness above the high voltage components. It also allows flexibility in the work of design and manufacture due to its modularity, while avoiding a bulky and expensive input transformer, regarding the conventional technology. Compared with other types of topologies, advantageous with a limited number of levels, the modular multilevel converter seems to be more suited for medium and high voltage applications, which are dependent on the association of power components. However, for variable speed drive application, a certain number of technological challenges have been highlighted, given the specific functional characteristics of the modular multilevel inverter and the constraints imposed by the very low frequency operation. On the one hand, for the normal operation of a multilevel modular converter, the waveform of the internal currents, in contrast to other types of topologies, is not symmetrical due to the distribution of the direct current in each phase leg. This may entail a significant disparity in terms of heat dissipation within the switching devices constituting a sub-module. Therefore, the problem of thermal management of active components is emphasized in the use of a modular multilevel converter. With the choice of a 3D packaging technology, interconnection by bumps, the ability to cool the semiconductor chips through the both sides of a module offers better cooling effects and a new perspective to design the power module for the studied structure. The concept of laying chips on both the two substrates of module without facing each other provides overall balanced dissipation in the space and permit to overcome the unbalanced heat distribution induced by bumps. Combined with the sharing of a switch by two chips in parallel, the proposal of the new architecture for 3D power module also aims to balance the double-sided cooling in the time range. Indeed, for the very low frequency operation, the switches operate in unsteady state where each switch has its own thermal behavior, it is no longer possible to compensate the thermo-mechanical constraints over each component with the help of the others, as in steady state and with a planar chips positioning scheme. On the other hand, from a systemic point of view, the control strategy and the dimensioning of floating capacitors of modular multilevel inverter are two interrelated aspects. Because the floating capacitors, having the role of energy sources, are loaded / unloaded through the modulation period, which causes very high voltage ripples across those capacitors with a very low frequency. This will destabilize the inverter and even provoke the destruction of components by approaching too high voltage levels. Thus, wisely designed controllers reduce unwanted ripples and, furthermore, allow embarking much smaller capacity in the system, as they are inversely proportional to the voltage ripple. In order to have a thorough understanding on the dynamics governing the modular multilevel converter, a comprehensive dynamic model based on state-space representation was established. Although this representation is limited to the second harmonic of characteristic variable, it allows a faithful interpretation of the conversion mechanism without using energy models, more complex to operate, and control laws can also be proposed and their effectiveness around the nominal frequency has been underlined. Concerning the very low frequency operations, another solution has been proposed and is ongoing patent pending.
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Packaging de composants grand gap haute température et haute tension / High temperature high voltage packaging of wide-band gap componentsRoske, Laurent 27 April 2015 (has links)
En électronique de puissance, un des principaux axes de recherche, concerne la montée en température. L'encapsulation et la passivation du module de puissance constituent, sous cette contrainte, des verrous technologiques. En effet, les matériaux polymères habituellement utilisés ne peuvent plus satisfaire des exigences en température fixée dans notre étude à 350°C sans pertes importantes de leurs propriétés diélectriques. L'isolation gazeuse a été alors envisagée et quelques résultats encourageants ont été dégagés. Le seuil d'apparition des décharges dans des gaz est étudié en vue de leur utilisation dans des modules de puissance à haute température. Deux gaz ont été sélectionnés pour leurs propriétés diélectriques et leurs GWP faibles : l'octafluoropropane (C3F8) et l'octafluorocyclobutane (c-C4F8), l'azote (N2) faisant référence pour comparaison. Au préalable, une étude sur les céramiques les plus utilisées à haute température est réalisée. Cette étude montre un changement du mécanisme de conduction de l'alumine et de l'AlN passant d'un régime capacitif à un régime résistif et modifiant au passage les propriétés de surface en facilitant l'écoulement des charges dans le volume du matériau tandis que le Si3N4 conserve un comportement capacitif et les charges en surface même à haute température. L'échauffement local des gaz met en évidence une diminution du seuil d'apparition des décharges avec la température et ce quel que soit le gaz étudié. La modification de la distance inter-électrodes permet de diminuer la variation du seuil d'apparition avec la température pour de faibles distances. Des expériences complémentaires ont été menées afin de comparer ces résultats à ceux obtenus lors d'un chauffage global. L'utilisation de gaz dans des packaging de puissance s'avère donc prometteuse mais demande une meilleure compréhension et maîtrise des mécanismes en jeu. / In power electronics, one of the main research topics concerns high temperature operation of the components. Under such a constraint, the encapsulation and the passivation of the semiconductors devices in power module appear as physical and technological bottleneck. As a matter of fact, usual polymeric materials are unable to endure the temperature requirements set out in our study (350 °C) without significant loss of their dielectric properties. Therefore, gas insulation is considered and encouraging results have been obtained. The Discharges Inception Voltage is studied for different gases that could be used in high temperature power modules. Thanks to their dielectric properties and their low GWP, two gases have been selected: octafluoropropane (C3F8) and octafluorocyclobutane (c-C4F8), nitrogen (N2) being used as reference in this study. In a first step, the high temperature behaviors of the most widely used substrate materials (ceramics) are studied. A change of the conduction mechanism from a pure capacitive behavior (at low temperature) to a pure resistive one (at high temperature) is observed for both alumina and AlN samples. On the contrary, Si3N4 remains capacitive whatever the temperature. Such a behavior has an impact on the charges located at the surface. They disappear quickly for the two formers while they slowly decrease for the later. The field reinforcement associated to their existence and its impact on the DIV will not be the same. Whatever the gas under study, a local heating leads to a decrease in the DIV with temperature. A decrease of the distance between the two electrodes, leads to a decrease of the DIV changes vs Temperature. These results are compared to the measurements performed when the samples were uniformly heated. The use of gas in power packaging seems to be promising but it still needs a better understanding of the mechanisms involved.
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Mécanismes moléculaires gouvernant la sélection et l'encapsidation de l'ARN génomique du VIH-1 : l’encapsidation sélective de l’ARN génomique du VIH-1 / Molecular mechanisms governing the selective encapsidation of HIV-1 genomic RNAWassim, Ekram 26 January 2012 (has links)
La sélection de l’ARNg des rétrovirus repose sur des interactions entre le domaine nucléocapside (NC) du précurseur Gag et des régions de l’ARN viral appelées ψ (ou Psi) localisées dans la région 5’ non traduite (5’-UTR) de l’ARNg et/ou dans le début du gène gag.Malgré des nombreuses études, les mécanismes moléculaires gouvernant l’incorporation de l’ARNg dans les particules virales en cours d’assemblage sont encore mal compris. La protéine Gag est notoirement sensible à la protéolyse et la plupart des études ont été menées avec une Gag dépourvue du domaine p6 (GagΔp6) qui ne reflètepas correctement les propriétés de fixation de la protéine Gag entière à l’ARNg. Les travaux réalisés aux cours de cette thèse nous ont permis de montrer que Pr55Gag et ses produits de maturation NCp15 et NCp7 sont capables de distinguer l’ARNg du VIH-1 des ARN viraux épissés. La stabilisation des formes dimériques ou la perturbation des interactions à longue distance n’ont aucune influence sur la reconnaissance spécifique de Gag pour l’ARNg. Par des expériences de mutagénèse dirigée et de compétition, nous avons montré non seulement que la dimérisation de l’ARNg et le motif SL1 (surtout sa boucle interne) joue un rôle crucial pour la fixation de Gag mais aussi que l’intégrité de la région Psi est indispensable pour une fixation optimale. Ces résultats nous ont amené à déterminer plus précisément l’empreinte de Gag sur l’ARNg et les résidus requis pour la fixation de Gag qui on confirmé le rôle crucial de SL1 comme le siganl major pour la reconnaissance spécifique de l’ARNg par le pr55Gag. / Packaging of HIV-1 genomic RNA (gRNA) is a highly regulated and selective process that leads to prefrential selection and packaging of dimeric gRNA from a cellular medium containing a large excess of cellular and spliced viral mRNAs. This event underlies interaction between the nucleocapsid domain in the context of the uncleaved Gag precursor and a Packaging signal located in the 5’ untranslated region (5’ UTR) of the gRNA and/or the beginning of gag gene. Despite a considerable effort, the molecular mechanisms beyond the selective encapsidation of HIV-1 gRNA is still unknown. To address this, we first characterized the relative affinities of Pr55gag to various HIV-1 RNA fragments (spliced and unspliced) by biochemical and spectroscopic approaches which all revealed that Pr55gag exhibits a higher binding affinity for viral gRNA than for viral spliced species. Interestingly, we noticed that Pr55Gag, through its nucleic acid chaperone activity, was able to stabilize the dimeric form of almost all viral RNA species (spliced and unspliced) suggesting that RNA dimermaturation does not allow the gRNA discrimination. Further characterization of specific Gag binding sites to short RNA fragments corresponding to the minimal packaging signal by competition experiments, inhibition of Gag/RNA interaction by antisense oligo-deoxynucleotides, as well as the detection of Pr55Gag RNA binding sites on gRNA by enzymatic and chemical footprinting confirmed the crucial role of SL1 (or DIS) as a specific binding site for Pr55Gag. Taken together, our results strongly suggest that SL1 and/or RNA dimerization is a specific recognition signal for Pr55Gag to specifically select and probably induce HIV-1 gRNA packaging.
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