abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

The contents of this work investigate the capability of integrating the PT in applications by invoking the ratio of the throughput power to volume represented by the term: power density. The fundamentals of the PT are introduced in chapter two. In chapter three, the fundamental limitations of the PT's capability of transferring power to the load are studied. There are three major limitations: temperature rise due to losses during operation, electromechanical limits of material, and interactions with output rectifier. The analysis and estimation are then verified by experiments and calculations implemented on three different PT samples fabricated from three different manufacturers. The subject of chapter four is the behavior of the PT's power amplifier. This chapter concentrates on two main amplifier topologies, optimized based on the simplicity of structure and minimization of components (passive and active): class D and class E amplifiers. The operational characteristics of these amplifiers with the PT are then comparison. Methods to track the optimum frequency and discontinuous working mode of the PT are proposed as the approaches to improve the energy transfer of the PT. In chapter five, prototypes of four devices using a PT are developed and introduced as illustrations of the integration of PTs into practical applications: an igniter for high intensity discharge (HID) lamps, high DC voltage power supplies, and electronic ballasts for LEDs, and stand-alone ionizers for food sterilizers. Some concluding statements and ideas for future works are located in the last chapter - chapter six.

Due to the power requirements for today's microprocessors, point of load converter packaging is becoming an important issue.   Traditional thermal management techniques involved in removing heat from a printed circuit board are being tested as today's technologies require small footprint and volume from all electrical systems.  While heat sinks are traditionally used to spread heat, ceramic substrates are gaining in popularity for their superior thermal qualities which can dissipate heat without the use of a heat sink.  3D integration techniques are needed to realize a solution that incorporates the active and components together.  The objective of this research is to explore the packaging of a high current, high power density, high frequency DC/DC converter using ceramic substrates to create a low profile converter to meet the needs of current technologies. One issue with current converters is the large volume of the passive components.  Increasing the switching frequency to the megahertz range is one way to reduce to volume of these components.  The other way is to fundamentally change the way these inductors are designed.  This work will explore the use of low temperature co-fired ceramic (LTCC) tapes in the magnetic design to allow a low profile planar inductor to be used as a substrate.  LTCC tapes have excellent properties in the 1-10 MHz range that allow for a high permeability, low loss solution.  These tapes are co-fired with a silver paste as the conductor.  This paper looks at ways to reduce dc resistance in the inductor design through packaging methods which in turn allow for higher current operation and better heavy load efficiency.  Fundamental limits for LTCC technologies are pushed past their limits during this work.  This work also explores fabrication of LTCC inductors using two theoretical ideas: vertical flux and lateral flux.  Issues are presented and methods are conceived for both types of designs.  The lateral flux inductor gives much better inductance density which results in a much thinner design. It is found that the active devices must be shielded from the magnetic substrate interference so active layer designs are discussed.  Alumina and Aluminum Nitride substrates are used to form a complete 3D integration scheme that gives excellent thermal management even in natural convection.  This work discusses the use of a stacked power technique which embeds the devices in the substrate to give double sided cooling capabilities.  This fabrication goes away from traditional photoresist and solder-masking techniques and simplifies the entire process so that it can be transferred to industry.  Time consuming sputtering and electroplating processes are removed and replaced by a direct bonded copper substrate which can have up to 8 mil thick copper layers allowing for even greater thermal capability in the substrate.  The result is small footprint and volume with a power density 3X greater than any commercial product with comparable output currents.  A two phase coupled inductor version using stacked power is also presented to achieve even higher power density. As better device technologies come to the marketplace, higher power density designs can be achieved.  This paper will introduce a 3D integration design that includes the use of Gallium Nitride devices.  Gallium Nitride is rapidly becoming the popular device for high frequency designs due to its high electron mobility properties compared to silicon.  This allows for lower switching losses and thus better thermal characteristics at high frequency.  The knowledge learned from the stacked power processes gives insight into creating a small footprint, high current ceramic substrate design.  A 3D integrated design is presented using GaN devices along with a lateral flux inductor.  Shielded and Non-Shielded power loop designs are compared to show the effect on overall converter efficiency.  Thermal designs and comparisons to PCB are made using thermal imaging.  The result is a footprint reduction of 40% from previous designs and power densities reaching close to 900W/in3. / Master of Science

Wide bandgap (WBG) devices and power electronic converters (PEC) that enable the dynamic control of energy and high-power density designs inevitably contain defects including sharp edges, triple points, and cavities, which result in local electric field enhancements. The intensified local electric stresses cause either immediate dielectric breakdown or partial discharge (PD) that erodes electrical insulators and accelerates device aging. With the goal of addressing these dielectric challenges emerging in power-dense applications, this dissertation focuses on 1) modeling the dielectric characteristics of supercritical fluids (SCFs), which is a new dielectric medium with high dielectric strength and high cooling capability; and 2) establishing the optimal fabrication conditions of electrets, which is a new dielectric solution that neutralizes locally enhanced electric fields. In this dissertation, the dielectric breakdown characteristics of SCFs are modeled as a function of pressure based on the electron scattering cross section data of clusters that vary in size as a function of temperature and pressure around the critical point. The modeled breakdown electric field is compared with the experimental breakdown measurements of supercritical fluids, which show close agreement. In addition, electrets are fabricated based on the triode-corona charging method and their PD mitigation performance is evaluated through a series of PD experiments. Electrets are fabricated under various charging conditions, including charging voltage, duration, polarity, and temperature with the goal of identifying the optimal condition that leads to effective PD mitigation. The PD mitigation performance of electrets fabricated based on these charging conditions is further assessed by investigating the impact of various power electronics voltage characteristics, including dv/dt, polarity, switching frequency, and duty cycle. Electret based electric field neutralization approach is further utilized in increasing the critical flashover voltage associated with the surface flashover voltage. Moreover, due to the high mechanical strength of epoxy composites at cryogenic temperatures, in this dissertation, epoxy-based electrets are fabricated as a solution to PD in high temperature superconducting cables. The experimental demonstrations conducted with electret in this dissertation is dedicated for the establishing the electret based electric field neutralization approach as a dielectric solution for the dielectric challenges in power electronics driven systems.

This thesis investigates the feasibility of using Silicon Carbide (SiC)-based multiphase inverters (MPIs) for transportation electrification applications. The research begins with a comprehensive review on the state-of-the-art of MPIs, focusing on voltage source inverters (VSIs) and nine-switch inverters (NSIs), with five-, six-, and nine-phase configurations. The quantitative and qualitative analyses demonstrate that the six-phase VSI is the most promising topology, offering reduced DC-capacitor requirements, lower cabling cost, and higher fault tolerance capability while maintaining the same efficiency and power device count of a three-phase VSI. The feasibility of the SiC-based six-phase inverter is further investigated at the vehicle level, where a vehicle model is developed to study the energy consumption under different drive cycles. The resulting indicate an 8% improvement in vehicle mileage and fuel economy of the SiC-based six-phase inverter compared to its Si-based counterpart. This thesis also examines the current and voltage stresses on the DC-bus capacitor in two-level six-phase VSIs. The study considers two configurations of load/winding spatial distribution: symmetric and asymmetric. Consequently, analytical formulas for the DC-bus capacitor current and voltage ripples are derived. Furthermore, simple capacitor sizing rules in six-phase VSIs with different load configurations are provided. The accuracy of the derived formulas is verified by simulation and experimental testing, and their boundary conditions are identified. Six-phase VSI supplying symmetric loads was found to yield the smallest capacitor size. Based on the foregoing technology review and analyses, a holistic design methodology for a 100 kW SiC-based six-phase traction inverter for an electric vehicle application is presented. The proposed methodology considers the device power level, where discrete SiC MOSFETs are utilized, and the DC-capacitor sizing, where a multi-objective optimization algorithm is proposed to find the most suitable capacitor bank. Mechanical and thermal design constraints are also explored to deliver a compact housing with an integrated coolant channel. The resultant inverter design from the proposed electrical-thermal-mechanical design methodology is prototyped and experimentally tested, demonstrating a 7% reduction in DC-capacitor volume and 21% reduction in cabling cost when compared to conventional three-phase inverters of the same volt-ampere rating. The peak power density of the prototype inverter is 70 kW/L, demonstrating a compact design. Besides, the proposed design is benchmarked against commercial six-phase inverter models, whereby the competitiveness of the proposed design is highlighted. Finally, the unique control aspects of six-phase electric motor drives are investigated to identify suitable controls strategies for various operating conditions. The study places special emphasis on high-speed operation and evaluates several overmodulation techniques. An adaptive flux-weakening control algorithm is also proposed for the six-phase motor drive, which significantly improves the DC-bus voltage utilization of the inverter when used in conjunction with overmodulation. Overall, this thesis provides a comprehensive study of SiC-based six-phase traction inverters and proposes a holistic design methodology that considers electrical, thermal, and mechanical aspects. The results demonstrate the feasibility and advantages of SiC-based six-phase traction inverters for electric vehicle applications. / Thesis / Doctor of Philosophy (PhD) / Electric cars are continuously challenged to meet regulatory mandates that become stricter by the day. This is driven by the need for a clean, reliable, affordable, and sustainable transportation system. In this research, a novel, more reliable, and cost-effective power control unit (PCU) is proposed. The PCU manages the power flow regulation between the battery and the motor(s). The proposed PCU employs the same number of devices as a traditional counterpart, yet in a more modular architecture that doubles the safety factor compared to the standard design. In fault scenarios where the traditional PCU would fail, the proposed PCU would continue operating at half power, allowing the driver and passengers to reach a safe destination before the car is repaired. Extensive analyses were undertaken to identify an optimal design in terms of performance, size, and cost. Then, an engineering prototype is constructed and tested on an electric drivetrain testbed. Finally, the prototype is benchmarked against commercial competitors in the market to establish its economical feasibility.

The development of high power density three-phase ac converter has been a hot topic in power electronics area due to the increasing needs in applications like electric vehicle, aircraft and aerospace, where light weight and/or low volume is usually a must. Many challenges exist due to the complicated correlations in a three-phase power converter system. In addition, with the emerging SiC device technology the operating frequency of the converter can be potentially pushed to the range from tens of kHz to hundreds of kHz at higher voltage and higher power conditions. The extended frequency range brings opportunities to further improve the power density of the converter. Technologies based on existing devices need to be revisited. In this dissertation, a systematic methodology to analyze and design the high power density three-phase ac converter is developed. All the key factors of the converter design are explored from the high density standpoint. Firstly, the criteria for the passive filter selection are derived and the relationship between the switching frequency and the size of the EMI filter is investigated. A function integration concept as well as the physical design approach is proposed. Secondly, a topology evaluation method is presented, which provides the insight into the relationships between the system constraints, operating conditions and design variables. Four topologies are then compared with the proposed approach culminating with a favored topology under the given conditions. Thirdly, a novel average model is developed for the selected topology, and used for devising a carrier-based control approach with simple calculation and good regulation performance. Fourthly, the converter failure mode operation and corresponding protection approaches are discussed and developed. Finally, a 10 kW three-phase ac/ac converter is built with the SiC devices. All the key concepts and ideas developed in this work are implemented in this hardware system and then verified by the experimental results. / Ph. D.

Today, every microprocessor is powered with a Voltage Regulator (VR), which is also known as a high current Point-of-Load converter (POL). These circuits are mostly constructed using discrete components, and populated on the motherboard. With this solution, the passive components such as inductors and capacitors are bulky. They occupy a considerable footprint on the motherboard. The problem is exacerbated with the current trend of reducing the size of all forms of portable computing equipment from laptop to netbook, increasing functionalities of PDA and smart phones. In order to solve this problem, a high power density POL needs to be developed. An integration solution was recently proposed to incorporate passive components, especially magnetic components, with active components in order to realize the needed power density for the POL. Today's discrete VR only has around 100W/in3 power density. The 3D integration concept is widely used for low current integrated POL. With this solution, a very low profile planar inductor is built as a substrate for the active components of the POL. By doing so, the POL footprint can be dramatically saved, and the available space is also fully utilized. This 3D integrated POL can achieve 300-1000W/in3 power density, however, with considerably less current. This might address the needs of small hand-held equipment such as PDA and Smart phone type of applications. It does not, however, meet the needs for such applications as netbook, laptop, desk-top and server applications where tens and hundreds of amperes are needed. So, although the high density integrated POL has been demonstrated at low current level, magnetic integration is still one of the toughest barriers for integration, especially for high current POL. In order to alleviate the intense thirst from the computing and telecom industry for high power density POL, the 3D integration concept needs be extended from low current applications to high current applications. The key technology for 3D integration is the low profile planar inductor design. Before this research, there was no general methodology to analyze and design a low profile planar inductor due to its non-uniform flux distribution, which is totally different as a conventional bulky inductor. A Low Temperature Co-fired Ceramic (LTCC) inductor is one of the most promising candidates for 3D integration for high current applications. For the LTCC inductor, besides the non-uniform flux, it also has non-linear permeability, which makes this problem even more complicated. This research focuses on penetrating modeling and design barriers for planar magnetic to develop high current 3D integrated POL with a power density dramatically higher than today's industry products in the same current level. In the beginning, a general analysis method is proposed to classify different low profile inductor structures into two types according to their flux path pattern. One is a vertical flux type; another one is a lateral flux type. The vertical flux type means that the magnetic flux path plane is perpendicular with the substrate. The lateral flux type means that the magnetic flux path plane is parallel with the substrate. This analysis method allows us to compare different inductor structures in a more general way to reveal the essential difference between them. After a very thorough study, it shows that a lateral flux structure is superior to a vertical flux structure for low profile high current inductor design from an inductance density point of view, which contradicts conventional thinking. This conclusion is not only valid for the LTCC planar inductor, which has very non-linear permeability, but is also valid for the planar inductor with other core material, which has constant permeability. Next, some inductance and loss models for a planar lateral flux inductor with a non-uniform flux are also developed. With the help of these models, different LTCC lateral flux inductor structures (single-turn structure and multi-turn structures) are compared systematically. In this comparison, the inductance density, winding loss and core loss are all considered. The proposed modeling methodology is a valuable extension of previous uniform flux inductor modeling, and can be used to solve other modeling problems, such as non-uniform flux transformer modeling. After that, a design method is proposed for the LTCC lateral flux inductor with non-uniform flux distribution. In this design method, inductor volume, core thickness, winding loss, core loss are all considered, which has not been achieved in previous conventional inductor design methods. With the help of this design method, the LTCC lateral flux inductor can be optimized to achieve small volume, small loss and low profile at the same time. Several LTCC inductor substrates are also designed and fabricated for the 3D integrated POL. Comparing the vertical flux inductor substrate with the lateral flux inductor substrate, we can see a savings of 30% on the footprint, and a much simpler fabrication process. A 1.5MHz, 5V to 1.2V, 15A 3D integrated POL converter with LTCC lateral flux inductor substrate is demonstrated with 300W/in3 power density, which has a factor of 3 improvements when compared to today's industry products. Furthermore, the LTCC lateral flux coupled inductor is proposed to further increase power density of the 3D integrated POL converter. Due to the DC flux cancelling effect, the size of LTCC planar coupled inductor can be dramatically reduced to only 50% of the LTCC planar non-coupled inductor. Compared to previous vertical flux coupled inductor prototypes, a lateral flux coupled inductor prototype is demonstrated to have a 50% core thickness reduction. A 1.5MHz, 5V to 1.2V, 40A 3D integrated POL converter with LTCC lateral flux coupled inductor substrate is demonstrated with 700W/in3 power density, which has a factor of 7 improvements when compared to today's industry POL products in the same current level. In conclusion, this research not only overcame some major academia problems about analysis and design for planar magnetic components, but also made significant contributions to the industry by successfully scaling the integrated POL from today's 1W-5W case to a 40W case. This level of integration would significantly save the cost, and valuable motherboard real estate for other critical functions, which may enable the next technological innovation for the whole computing and telecom industry. / Ph. D.

Three-phase voltage source converters(VSCs) have become the converter of choice in many ac medium and high power applications due to their many advantages, including low harmonics, high power factor, and high efficiency. Modular VSCs have also been a popular choice as building blocks to achieve even higher power, primarily through converter paralleling. In addition to high power ratings, paralleling converters can also provide system redundancy through the so-called (N+1) configuration for improved availability, as well as allow easy implementation of converter power management. Interleaving can further improve the benefit of paralleling VSCs by reducing system harmonic currents, which potentially can increase system power density. There are many challenges to implement interleaving in paralleled VSCs system due to the complicated relationships in a three-phase power converter system. In addition, to maximize the benefit of interleaving, current knowledge of symmetric interleaving is not enough. More insightful understanding of this PWM technology is necessary before implement interleaving in a real paralleled VSCs system. In this dissertation, a systematic methodology to analyze and design a paralleled three-phase voltage source converters with interleaving is developed. All the analysis and proposed control methods are investigated with the goal of maximizing the benefit of interleaving based on system requirement. The dissertation is divided into five sections. Firstly, a complete analysis studying the impact of interleaving on harmonic currents in ac and dc side passive components for paralleled VSCs is presented. The analysis performed considers the effects of modulation index, pulse-width-modulation (PWM) schemes, interleaving angle and displacement angle. Based on the analysis the method to optimize interleaving angle is proposed. Secondly, the control methods for the common mode (CM) circulating current of paralleled three-phase VSCs with discontinuous space-vector modulation (DPWM) and interleaving are proposed. With the control methods, DPWM and interleaving, which is a desirable combination, but not considered possible, can be implemented together. In addition, the total flux of integrated inter-phase inductor to limit circulating current can be minimized. Thirdly, a 15 kW three phase ac-dc rectifier is built with SiC devices. With the technologies presented in this dissertation, the specific power density can be pushed more than 2kW/lb. Fourthly, the converter system with low switching frequency is studied. Special issues such as beat phenomenon and system unbalance due to non-triplen carrier ratio is explained and solved by control methods. Other than that, an improved asymmetric space vector modulation is proposed, which can significantly reduce output current total harmonic distortion (THD) for single and interleaved VSCs system. Finally, the method to protect a system with paralleled VSCs under the occurrence of internal faults is studied. After the internal fault is detected and isolated, the paralleled VSCs system can continue work. So system reliability can be increased. / Ph. D.

The continual development of high-power-density power electronic converters is driven particularly by modern transportation applications like electrical vehicles and more electric aircraft where the space and carrier capability is limited. However, there are several challenges related to transportation applications such as fault tolerance for safety concern, high temperature operation in extreme environments and more strict electromagnetic compatibility requirement. These challenges will increase difficulties for more electrical system adoption in the transportation applications. In this dissertation, comprehensive methodologies including more efficient energy storage solution, better power electronics devices capability, better packaging performance and more compact EMI filter design are analyzed and proposed for the goal of high power density converter design in transportation applications. / Ph. D.

This work explores how GaN devices and advanced control can improve the power density of battery chargers for the plug-in hybrid electric vehicle. Gallium nitride (GaN) devices are used to increase switching frequency and shrink passive components. An innovative DC link reduction technique is proposed and several practical design issues are solved. A multi-chip-module (MCM) approach is used to integrate multiple GaN transistors into a package that enables fast, reliable, and efficient switching. The on-resistance and output charge are characterized. In a double pulse test, GaN devices show fast switching speed. The loss estimation based on the characterization results shows a good match with the measurement results of a 500 kHz GaN-based boost converter. Topology selection is conducted to identify candidates for the PHEV charger application. Popular topologies are reviewed, including non-isolated and isolated solutions, and single-stage and two-stage solutions. Since the isolated two-stage solution is more promising, the topologies consisting of an AC/DC front-end converter and an isolated DC/DC converters are reviewed. The identified candidate topologies are evaluated quantitatively. Finally, the topology of a full bridge AC/DC plus dual active bridge DC/DC is selected to build the battery charger prototype for fixed switching-frequency, low loss, and low realization complexity. The DC link capacitor is one of the major power density barriers of the charger, as its size cannot be reduced by increasing the switching frequency. This work proposed a charging scheme to reduce the DC link capacitance by balancing the ripple power from input and output given that the double-line-frequency current causes minor impact to the battery pack in terms of capacity and temperature rise. An in-depth analysis of ripple power balance, with converter loss considered, unveils the conditions of eliminating the low-frequency DC link capacitors. PWM-zero-off charging where the battery is charged by a current at double-line-frequency and DC/DC stage is turned off at the zero level of the waveform, is also proposed to achieve a better tradeoff between the DC link capacitor size and the charger efficiency. The practical design issues are outlined and the solutions are given at different levels of implementations, including the full bridge building block, the AC/DC stage, and the DC/DC stage. The full bridge section focuses on the solution of a reliable driving and sensing circuitry design. The AC/DC stage portion stresses the modulator improvement, which solves the often-reported issues of the current spike at the zero-crossing of the line voltage for the high frequency totem-pole bridgeless converter. In the DAB section, analytical expressions are given to model the converter operation at various operating conditions, which match well with the measurement results. The overall charging-system operation including the seamless transition of bi-directional power flow and the charging-profile control is verified on a laboratory GaN charger prototype at 500 kHz and 1.8 kW with an efficiency of 92.4%. To push the power density, some bulky components including the control board, the cooling system, and the chassis are redesigned. Together with other already-verified building blocks including full bridges, magnetics, and capacitors, a high-density mock-up prototype with 125 W/in3 power density is assembled. / Ph. D.