Depuis la première génération de téléphone mobile, de nombreuses fonctions et outils ont été intégrés dans nos terminaux. Il y a vingt ans, nous utilisions nos téléphone pour émettre des appels et envoyer/recevoir des messages. Aujourd’hui, l’accès à internet, la radio, l’appareil photo, des jeux et de la musique sont des fonctionnalités que l’on retrouve dans nos téléphones mobiles.Dans un contexte de téléphonie pouvant adresse plusieurs standards, l’objectif de cette thèse est de concevoir et de réaliser l’implémentation d’une architecture capable d’améliorer la linéarité de notre émetteur pour le standard 3G, utilisant des composants analogiques et numériques. Pour cela, notre étude se concentrera sur l’amélioration de la linéarité, tout en maintenant une consommation la plus faible possible mais également tout en évitant d’augmenter la taille d’une puce 3G. Nous allons démontrer qu’il est possible d’intégrer une technique de linéarisation tout en maintenant une consommation et une surface en silicium.Le premier chapitre présente différentes architectures d’émetteurs et des techniques de linéarisation avec leurs avantages et inconvénients. Il est également présenté des moyens d’évaluer l’efficacité d’un émetteur par des simulations ou des mesures. L’objectif de cette partie est de choisir une technique de linéarisation à laquelle nous associerons une architecture d’émetteur afin de répondre le plus rigoureusement à notre application et ces contraintes émanant.Le second chapitre détaille le fonctionnement du système complet, la partie numérique et la partie analogique, s’appuyant sur des études théoriques. Nous commencerons en détaillant les contraintes et les précautions qui doivent être prises en compte par le concepteur afin d’étudier l’instabilité et le bruit produit par l’émetteur. Nous décrierons alors deux algorithmes numériques permettant de réaliser la correction des signaux. Des simulations au niveau système de la boucle Cartésienne seront également présenté utilisant, dans un premier temps un amplificateur de puissance idéal, pour ensuite utilisé un amplificateur de puissance réalisé en technologie BiCMOS, et finalement un amplificateur de puissance conçu en technologie CMOS, qui est celle choisie pour notre étude.Le troisième chapitre présente la synthèse de la partie numérique en technologie CMOS des deux algorithmes précédemment cités, elle prend en compte toutes les étapes ; du code VHDL jusqu’au layout, permettant de réaliser un circuit numérique. Ensuite, il est décrit chaque composant de la boucle cartésienne, avec leurs propres simulations ou mesures. De plus, il est important de garder à l’esprit que l’objectif de cette thèse repose sur l’intégration du système complet (partie analogique et numérique) en technologie CMOS 65nm de STMicroelectronics, démontrant ainsi la faisabilité de la solution.Dans un premier temps, nous décrirons la partie numérique permettant de réaliser les étapes de correction de phase et de soustraction des signaux en technologie ASIC. L’algorithme de CORDIC a pour avantage de minimiser la consommation et l’occupation en Silicium de la partie analogique. Par la suite, l’architecture et les spécifications de chaque brique de base constituant la partie analogique seront présentées. Dans notre cas, la chaîne directe est composée de filtres, de mélangeurs, et d'un amplificateur de puissance. Notre objectif est de réaliser ces trois fonctions avec le minium de consommation et une surface du circuit la plus faible possible, ceci permettant une intégration plus aisée.Finalement, les simulations système seront présentées utilisant le logiciel de simulation ADC (Advanced Design Software) d’Agilent pour la partie analogique. Des co-simulations ont été réalisées sur le système complet, utilisant SystemVue pour la partie numérique. Les simulations réalisant ADS nous ont fourni les performances de chaque brique de base s’appuyant sur les caractéristiques des transistors. / Since the first generation of mobile phones, a lot of functions, standards and tools have been integrated on handsets. Twenty years ago, consumers could use their mobile phones only to call and to send messages. Nowadays, internet access, radio, cameras, games and music are included and available as options for every mobile phone.All of these new services make the cost of production for a cellular phone more expensive. Despite that, industry has to find a solution to maintain their products the most attractive as possible including the large range of integrated functions.In the context of interaction with other standards, the aim of this thesis is to design and implement a chipset able to improve the linearity of a transmitter for third generation mobile phones, using both digital and analog technologies. For this purpose, the study will focus on the improvement of the linearity, keeping the consumption and the die area of the circuit as small as possible. We will prove that linearization on an integrated circuit is possible with almost the same consumption and die area occupation compared to a classic transmitter.The first chapter presents the different architectures used for a transmitter and various linearization techniques with their advantages and drawbacks. Some metrics are also presented in order to evaluate these architectures. The goal of this part is to choose a linearization technique associated to a transmitter in order to fit with our application and constraints.The second chapter explains the complete system, digital and analog parts, with theoretical studies. We will start by detailing the constraints and precautions that must be taken into account by the designer to study the instability and the noise generated by the transmitter. We will describe how two algorithms make signal corrections. In the last part we will show system level simulations of the Cartesian Feedback using, first, an ideal power amplifier (PA), then, a PA in a BiCMOS technology, and finally, a PA in a CMOS technology that will be used for the final integrated circuit.The third and last chapter shows the digital synthesis in a CMOS technology of the two algorithms previously mentioned, considering all steps, from the VHDL code until the layout of the digital part. We will describe and simulate each analog building block of the Cartesian Feedback, with the measurement results for some of them. Each chapter will be working towards the goal of this study, demonstrated in this part: to make an integrated system, with its complete solution and simulations.This chapter presents the integration of the analog and digital Cartesian Feedback described previously in 65nm CMOS technology from STMicroelectronics. First, the digital part generating the phase correction and subtraction will be shown in ASIC technology, with a CORDIC algorithm to reduce its consumption and size. Secondly, the architecture and specification of building blocks will be shown. In our case, the direct path is composed of filters, RF modulator and a Power Amplifier. Our objective is to design these three functions to minimize the consumption and the silicon area of the integrated architecture. Finally, system level simulations will be presented using the ADS (Advanced Design Software) from Agilent for the analog part. Co-simulations have been done to analyze the whole system, with SystemVue for the digital part. The simulations using ADS will provide the performance of each building block on the transistors level.

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This Diploma thesis deals with methods that increase efficiency of transistor amplifiers. In the first part of the thesis we describe theoretical background of the constructions of power amplifiers. At first we deal with the classical method that is concerned with a change of position of the static operating point. Secondly we cover the multi harmonic manipulation method (MHM). This method is concerned with a proper loading of particular harmonic components and consequential shaping of voltage runs and currents on the collector. In the second part of the work we have constructed the substitutes of particular accesses. Constructed classes are AB, F and FMHM. Basic S parameters and output signal spectrum were measured. We can see from the calculated efficiencies AB = 11%, F = 16% a Fmhm = 18%, big increase of efficiency F and FMHM only by changing output network.

In this paper we will deal involving short-wave radio station and its control by the sequencer. Mostly it will be a time delay of the PA and the antenna switching relay in the transmitter (TX) to receiver (RX) side. Time delays will be controlled programmatically using ATmega 16 microprocessor, which will form part of the main control sequencer. The delay will set the total time of keying in messages, when we take into account the loss due to delayed first symbol. Keying will be done from several sources, among the main sources will be ordered from keying the radio, telegraph keys, and PC. The transmission signal is used amplitude modulation (SSB) in the CB zone.

This work is focused on design of L band power amplifier. First, the design of the amplifier is substantiated by necessary theoretical basics of RF power amplifiers. Then, after comparsion of availible RF power amplifiers concepts, the doherty power amplifier is chosen as a suitable type. Design of the amplifier is focused on the linearity and efficiency. AWR design program is used for simulation of the amplifier. Amplifier is then realized and parameters are measured. Measured results are then discussed and evaluated. This work proposes design of the linear doherty amplifier for modern communications systems.

abstract: A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out- put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

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No description available.

CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class E power amplifier is designed and laid out using TSMC 0.18 µm RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate selfheating effects under different localized heating situations. iv Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called ¿future internet¿ paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.