CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class E power amplifier is designed and laid out using TSMC 0.18 µm RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate selfheating effects under different localized heating situations. iv Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called ¿future internet¿ paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

High efficiency is an essential requirement for any system, where the energy can be saved with full retention of system performance. The power amplifier in modern mobile communications system consumes most of the supplied power through the dissipated power and the required cooling systems. However, as new services were added as features for the developed mobile generations, the required data rate has increased to fulfil the new requirements. In this case, the data should be sent with the allocated bandwidth, so complex modulation schemes are used to utilise the available bandwidth efficiently. Nevertheless, the modulated signal will have a Peak to Average Power Ratio (PAPR) which increases as the modulation complexity is increasing. In this case, the power amplifier should be backed off and designed to provide good linearity and efficiency over high PAPR. Among the efficiency enhancement techniques, the Doherty technique (Load modulation technique) is the simplest one, where no additional circuity nor signal processing is required. In this work, the theory of load modulation amplifiers is investigated through two asymmetrical Doherty Power Amplifiers (DPA) targeting 3.3-3.5 GHz were designed and fabricated using two transistors (25 W and 45 W). In addition, more compact load modulation amplifiers targeting sub 6-GHz bandwidth of 5G specifically 3.4-3.8 GHz is discussed including the theory of implementing these amplifiers, where different amplifier capabilities are explored. Each amplifier design was discussed in detail, in which the input and output matching networks were designed and tested in addition to the design of the stability circuit to make sure that the amplifier is stable and working according to the specified requirements. The fabricated circuits were evaluated practically using the available instrument test, whereas Microwave Office software was used for the simulation purpose, each amplifier was designed separately, where all the designed amplifiers were able to provide the targeted efficiency at different back-off power points. Besides, some additional factors that affect the designed load modulation amplifiers such as the effect of the harmonics at the back-off and mismatching the amplifier is discussed. / European Union’s Horizon 2020 research and innovation programme (SECRET)

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Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance. / Doctor of Philosophy / To keep up with the ever-growing demand for exchanging information through a radio frequency (RF) wireless network, the specification of the communication hardware (i.e. transmitter and receiver) must be improved as the bottleneck of the system. This has been motivating engineers to introduce new and efficient approaches toward this goal. In this dissertation however, we study three aspects of the circuit design. First, variation in the ambient temperature can significantly degrade the performance of the communication system. Therefore, we study these variations on the performance of the transmitter at high temperature (i.e. above 200 C). Then, the temperature compensation approaches are introduced to minimize the impact of the temperature changes. The effectiveness of the introduced techniques are validated through measurements of the prototyped transmitter. Second, signal generators (i.e. oscillators) are the inseparable blocks of the transmitters. Phase noise is one of the most important specifications of the oscillators that can directly be translated to the quality and data rate of the communication. A new oscillator structure targeting ultra-low phase noise is introduced in the second part of this dissertation. The designed oscillator is fabricated and measured to evaluate its performance. Finally, a new polar transmitter architecture for low power applications is introduced. The transmitter offers design simplicity and compact size compared to other polar transmitter architectures while high performance.

Yes / This paper presents an approach to implement an automatically tuning antenna for optimising power transfer suitable for software defined radio (SDR). Automatic tuning is accomplished using a closed loop impedance tuning network comprising of an impedance sensor and control unit. The sensor provides the control unit with data on the transmit or receive power, and the algorithm is used to impedance of a T-network of LC components to optimize the antenna impedance to maximise power transmission or reception. The effectiveness of the proposed tuning algorithm in relation to impedance matching and convergence on the optimum matching network goal is shown to be superior compared with the conventional tuning algorithm. / This work is partially supported by innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E022936/1

As the demand for wireless electronics is increasing, more and more gadgets are connected wirelessly and devices are being improved constantly. The need of the new research and development for advance electronics with high performances is the priority. The data transfer rates are improved for faster communication and better efficiency is to reduce the battery consumption in handheld devices. This thesis presents three single-stage power amplifiers (PAs): class-AB, class-F and inverse class-F (class-F-1) at 28 GHz. The PAs have identical input networks: input matching, base DC feed, and base stabilizing networks. At the load side, there is a different load network for each PA. Class-AB PA load network has a single inductor with a parasitic capacitor to create a resonance at 28GHz. Class-F PA load network is composed of a parallel network (one LC tank in series with an inductor) and a series network (one 3f0-resonance LC tank in series with a capacitor) to create a multi-resonance load network. Class-F-1 load network is composed of a parallel network (two LC tank in series with an inductor) and a series network (one 2f0-resonance LC tank in series with a capacitor) to have a multi-resonance network. The main purpose of using multi-resonance load networks in class-F and class-F-1 is to shape the collector currents and voltages in order to achieve the highest efficiency possible. The chosen bias point is VCE=2.3V and ICE~12mA. As the results, class-AB PA achieves the peak PAE of 44%, 15 dBm OP-1dB, >19 dBm Psat , and 10 dB Gp. Class-F PA achieves the peak PAE of 46%, 14.5 dBm OP-1dB, ~18 dBm Psat , and 10 dB Gp. Class-F-1 PA achieves the peak PAE of 45%, 15.1 dBm OP-1dB, >18 dBm Psat , and 10 dB Gp.. In order to compare the linearity performances among three PA classes, a two-tone signal and a modulated signal with different modulation schemes (QPSK, 16QAM, 64QAM, and 256QAM) are applied to the PAs to produce IM3, ACPR, and EVM. After the analysis and comparison on efficiency and linearity, class-F PA gives the highest efficiency but has the worst linearity while class-AB has the best linearity but has the worst efficiency among three. Class-F-1 PA results lies in the middle of two other classes in term of efficiency and linearity. / Master of Science / As the demand for wireless electronics is increasing, more and more gadgets are connected wirelessly and devices are being improved constantly. The data transfer rates are improved for faster communication and better efficiency is to reduce the battery consumption in handheld devices. A power amplifier is a very essential component in many microwave and millimeterwave systems. This thesis presents the designs of three different RF power amplifiers (PAs), which belongs to three different types of PAs: class-AB PA, class-F PA, and inverse class-F (class-F^-1) PA. Each PA is designed to show distinct behaviors at a very high frequency around 28 GHz. Some portions of the designs are very identical among three classes. Three PAs have different circuit portions at the output side, which affect the performances of the PAs. There exists a capacitance from the transistor architecture, so called parasitic capacitance (C_P). In class-AB PA output, a single inductor is used to create a resonance with C_P. In class-F and class-F^-1 PA outputs, the combination of inductors and capacitors results in resonances at fundamental frequency (f₀), second harmonic (2f₀), and third harmonic (3f₀) depending on the impedance requirements of each PA. The main purpose is to shape the voltage and current waveforms in order to obtain the highest performances possible. The voltage and current supplied to the PA are chosen to achieve high power and efficiency at the output of the PAs. The most important parameters in PA design are efficiency and linearity. Efficiency is the effectiveness of the DC power conversion process from supplies into microwave power, which can be expressed as the ratio between output power and supplied DC power. Linearity is a term synonymous with fidelity in an audio amplifier. The term refers to the essential job of an amplifier to increase the power level of an input signal without otherwise altering the content of the signal. After the analysis and comparison on power efficiency and linearity, class-F PA gives the highest efficiency but has the worst linearity while class-AB has the best linearity but has the worst efficiency among three. Class-F^-1 PA results lies in the middle of two other classes in term of efficiency and linearity.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / A conventionally designed radio frequency amplifier operated in its linear region exhibits low DC to RF conversion efficiency. Typically, for a power amplifier designed for digital modulation applications, the amplifier is operated “backed-off” from its P1dB point by a factor of 10 or -10 dB. The typical linear amplifier is biased for either Class A or Class A/B operation depending on the acceptable design trade-offs between efficiency and linearity between these two methods. A novel design approach to increasing the efficiency of a linear RF power amplifier using a modified Odd-Way Doherty technique is presented in this paper. The design was simulated, built and then tested. The design yields improvements in efficiency and linearity.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / In RF power transistor characterisation, the designer is confronted with low impedance measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in metal-ceramic packages of which the lead widths vary with power capability. This thesis presents a high-quality fixture design with low impedance TRL calibration standards for characterisation of an LDMOS transistor. Pre-matching networks are used to transform to the low impedance environment. Since these pre-matching networks are independent of the termination impedance, the low impedance port can always be designed to comply with the same dimension as the device which is being measured.