Aquesta Tesi Doctoral se centra en el disseny d'un nou linealitzador de Predistorsió Digital (Digital Predistortion - DPD) capaç de compensar la dinàmica i els efectes no lineals introduïts pels Amplificadors de Potència (Power Amplifiers - PAs). Un dels trets més rellevants d'aquest nou predistorsionador digital i adaptatiu consisteix en ser deduïble a partir d'un model de PA anomenat Nonlinear Auto-Regressive Moving Average (NARMA). A més, la seva arquitectura multi-LUT (multi-Taula) permet la implementació en un dispositiu Field Programmable Gate Array (FPGA).La funció de predistorsió es realitza en banda base, per tant, és independent de la banda freqüencial on es durà a terme l'amplificació del senyal de RF, el que pot resultar útil si tenim en compte escenaris multibanda o reconfigurables. D'altra banda, el fet que aquest DPD tingui en compte els efectes de memòria introduïts pel PA, representa una clara millora de les prestacions aconseguides per un simple DPD sense memòria. En comparació amb d'altres DPDs basats en models més computacionalment complexos, com és el cas de les xarxes neuronals amb memòria (Time-Delayed Neural Networks - TDNN), la estructura recursiva del DPD proposat permet reduir el nombre de LUTs necessàries per compensar els efectes de memòria del PA. A més, la seva estructura multi-LUT permet l'escalabilitat, és a dir, activar or desactivar les LUTs que formen el DPD en funció de la dinàmica que presenti el PA.En una primera aproximació al disseny del DPD, és necessari identificar el model NARMA del PA. Un dels majors avantatges que presenta el model NARMA és la seva capacitat per trobar un compromís entre la fidelitat en l'estimació del PA i la complexitat computacional introduïda. Per reforçar aquest compromís, l' ús d'algoritmes heurístics de cerca, com són el Simulated Annealing o els Genetic Algorithms, s'utilitzen per trobar els retards que millor caracteritzen la memòria del PA i per tant, permeten la reducció del nombre de coeficients necessaris per caracteritzar-la. Tot i així, la naturalesa recursiva del model NARMA comporta que, de cara a garantir l'estabilitat final del DPD, cal dur a terme un estudi previ sobre l'estabilitat del model.Una vegada s'ha obtingut el model NARMA del PA i s'ha verificat l'estabilitat d'aquest, es procedeix a l'obtenció de la funció de predistorsió a través del mètode d'identificació predictiu. Aquest mètode es basa en la continua identificació del model NARMA del PA i posteriorment, a partir del model obtingut, es força al PA perquè es comporti de manera lineal. Per poder implementar la funció de predistorsió en la FPGA, cal primer expressar-la en forma de combinacions en paral·lel i cascada de les anomenades Cel·les Bàsiques de Predistorsió (BPCs), que són les unitats fonamentals que composen el DPD. Una BPC està formada per un multiplicador complex, un port RAM dual que actua com a LUT (taula de registres) i un calculador d'adreces. Les LUTs s'omplen tenint en compte una distribució uniforme dels continguts i l'indexat d'aquestes es duu a terme mitjançant el mòdul de l'envoltant del senyal. Finalment, l'adaptació del DPD consisteix en monitoritzar els senyals d'entrada i sortida del PA i anar duent a terme actualitzacions periòdiques del contingut de les LUTs que formen les BPCs. El procés d'adaptació del contingut de les LUTs es pot dur a terme en la mateixa FPGA encarregada de fer la funció de predistorsió, o de manera alternativa, pot ser duta a terme per un dispositiu extern (com per exemple un DSP - Digital Signal Processor) en una escala de temps més relaxada. Per validar l'exposició teòrica i provar el bon funcionalment del DPD proposat en aquesta Tesi, es proporcionen resultats tant de simulació com experimentals que reflecteixen els objectius assolits en la linealització del PA. A més, certes qüestions derivades de la implementació pràctica, tals com el consum de potència o la eficiència del PA, són també tractades amb detall. / This Ph.D. thesis addresses the design of a new Digital Predistortion (DPD) linearizer capable to compensate the unwanted nonlinear and dynamic behavior of power amplifiers (PAs). The distinctive characteristic of this new adaptive DPD is its deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA behavioral model and its particular multi look-up table (LUT) architecture that allows its implementation in a Field Programmable Gate Array (FPGA) device.The DPD linearizer presented in this thesis operates at baseband, thus becoming independent on the final RF frequency band and making it suitable for multiband or reconfigurable scenarios. Moreover, the proposed DPD takes into account PA memory effects compensation which representsan step forward in overcoming classical limitations of memoryless predistorters. Compared to more computational complex DPDs with dynamic compensation, such Time-Delayed Neural Networks (TDNN), this new DPD takes advantage of the recursive nature of the NARMA structure to relax the number of LUTs required to compensate memory effects in PAs. Furthermore, its parallel multi-LUT architecture is scalable, that is, permits enabling or disabling the contribution of specific LUTs depending on the dynamics presented by a particular PA.In a first approach, it is necessary to identify a NARMA PA behavioral model. The extraction of PA behavioral models for DPD linearization purposes is carried out by means of input and output complex envelope signal observations. One of the major advantages of the NARMA structure regards its capacity to deal with the existing trade-off between computational complexity and accuracy in PA behavioral modeling. To reinforce this compromise, heuristic search algorithms such the Simulated Annealing or Genetic Algorithms are utilized to find the best sparse delays that permit accurately reproducing the PA nonlinear dynamic behavior. However, due to the recursive nature of the NARMA model, an stability test becomes a previous requisite before advancing towards DPD linearization.Once the PA model is identified and its stability verified, the DPD function is extracted applying a predictive predistortion method. This identification method relies just on the PA NARMA model and consists in adaptively forcing the PA to behave as a linear device. Focusing in the DPD implementation, it is possible to map the predistortion function in a FPGA, but to fulfill this objective it is first necessary to express the predistortion function as a combined set of LUTs.In order to store the DPD function into a FPGA, it has to be stated in terms of parallel and cascade Basic Predistortion Cells (BPCs), which are the fundamental building blocks of the NARMA based DPD. A BPC is formed by a complex multiplier, a dual port RAM memory block acting as LUT and an address calculator. The LUT contents are filled following an uniform spacing procedure and its indexing is performed with the amplitude (modulus) of the signal's envelope.Finally, the DPD adaptation consists in monitoring the input-output data and performing frequent updates of the LUT contents that conform the BPCs. This adaptation process can be carried out in the same FPGA in charge of performing the DPD function, or alternatively can be performed by an external device (i.e. a DSP device) in a different time-scale than real-time operation.To support all the theoretical design and to prove the linearization performance achieved by this new DPD, simulation and experimental results are provided. Moreover, some issues derived from practical experimentation, such as power consumption and efficiency, are also reported and discussed within this thesis.

With the explosive growth of the wireless market, the demand for low-cost and highly-integrated radio frequency (RF) transceiver has been increased. Keeping up with this trend, complimentary metal-oxide-semiconductor (CMOS) has been spotlighted by virtue of its superior characteristics. However, there are challenges in achieving this goal, especially designing the transmitter portion. The objective of this research is to demonstrate the feasibility of fully integrated CMOS transmitter module which includes power amplifier (PA) and transmit/receive (T/R) switch by compensating for the intrinsic drawbacks of CMOS technology. As an effort to overcome the challenges, the high-power handling T/R switches are introduced as the first part of this dissertation. The proposed differential switch topology and feed-forward capacitor helps reducing the voltage stress over the switch devices, enabling a linear power transmission. With the high-power T/R switches, a new transmitter front-end topology - differential PA and T/R switch topology with the multi-section PA output matching network - is also proposed. The multi-stage PA output matching network assists to relieve the voltage stress over the switch device even more, by providing a low switch operating impedance. By analyzing the power performance and efficiency of entire transmitter module, design methodology for the high-power handling and efficient transmitter module is established. Finally, the research in this dissertation provides low-cost, high-power handling, and efficient CMOS RF transmitter module for wireless applications.

In this thesis, a parsimoniously parameterized digital predistorter is derived for linearization of the IQ modulation mismatch and the amplifier imperfection in the signal generator [1]. It is shown that the resulting predistorter is linear in its parameters, and thus they may be estimated by the method of least-squares. Spectrally pure signals are an indispensable requirement when the signal generator is to be used as part of a test bed. Due to the non-linear characteristic of the IQ modulator and power amplifier, distortion will be present at the output of the signal generator. The device under test was the IQ modulation mismatch and power amplifier deficiencies in the signal generator. In [2], the dynamic range of low-cost signal generators are improved by employing model based digital pre-distortion and the designed predistorter seems to give some improvement of the dynamic range of the signal generator. The goal of this project is to implement and verify the theory parts [1] using data program (Matlab) to improve the dynamic range of the signal generator. The design digital pre-distortion that is implemented in software so that the dynamic range of the signal generator output after predistortion is superior to that of the output prior to it. In this project, we have observed numerical problems in the proposed theory and we have found other methods to solve the problem. The polynomial model is commonly used in power amplifier modeling and predistorter design. However, the conventional polynomial model exhibits numerical instabilities when higher order terms are included, we have used the conventional and orthogonal polynomial models. The result shows that the orthogonal polynomial model generally yield better power amplifier modeling accuracy as well as predistortion linearization performance then the conventional polynomial model.

The design of power amplifiers within a circuit simulator requires a good non-linear model that accurately predicts the electormagnetic behaviour of the power transistor. In recent years, a certain class of large signal frequency-dependent black-box behavioural modeling techniques known as Poly-Harmonic Distortion (PHD) models has been devised to mimic the non-linear unmatched RF transistor. These models promise a good prediction of the device behaviour under multi-harmonic periodic continuous wave inputs. This thesis describes the capabilities of the PHD modeling framework and the theoretical type of behaviour that it is capable of predicting. Specifically, the PHD framework cannot necessarily predict the response of a broadband aperiodic signal. This analysis will be performed by deriving the PHD modeling framework as a simplification of the Volterra series kernel functions under the assumption that the power transistor is operating under continuous periodic multi-harmonic voltage and current signals in a stable circuit. A PHD model will be seen as a set of describing functions that predict the response of the Device Under Test (DUT) for any given non-linear periodic continuous-wave inputs that have a specific fundamental frequency. Two popular implementations of PHD models that can be found in the literature are the X-parameter and Cardiff models. Each model formulates the describing functions of the general PHD model differently. The mathematical formulation of the X-parameter and Cardiff models will be discussed in order to provide a theoretical ground for comparing their robustness. The X-parameter model will be seen as the first-order Taylor series approximation of the PHD model describing functions around a Large Signal Operating Point (LSOP) of the device under test. The Cardiff large-signal model uses Fourier series coefficient functions that vary with the magnitude of the large signal(s) as the PHD model describing functions. This thesis will provide a breakdown of the measurement procedure required for the extraction of these models, the challenges involved in the measurement, as well as the mathematical extraction of the model coe cients from measurement data. As each of these models contain have extended versions that enhance the predictive capability of the model under stronger nonlinear modes of operation, a comparison is used to represent the cost of increasing model accuracy as a function of the increasing model complexity for each model. The order of complexity of each model can manifest itself in terms of the mathematical formulation, the number of parameters required and the measurement time that is required to extract each model for a given DUT. This comparison will fairly assess the relative strengths and weaknesses of each model.

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply.

The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation. The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done. The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W. A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.

In recent years, tremendous growth of the wireless market can be defined through the following words: smartphone and high-data rate wireless communication. This situation gives new challenges to RF power amplifier design, which includes high-efficiency, multi-band operation, and robustness to antenna mismatch conditions. In addition to these issues, the industry and consumers demand a low-cost small-sized wireless device. A fully integrated single-chip CMOS transceiver is the best solution in terms of cost and level of integration with other functional blocks. Therefore, the effective approaches in a CMOS process for the abovementioned hurdles are highly desirable. In this dissertation, the new challenges are overcome by introducing adaptability to a CMOS power amplifier. Meaningful achievements are summarized as follows. First, a new CMOS switched capacitor structure for high power applications is proposed. Second, a dual-mode CMOS PA with an integrated tunable matching network is proposed to extend battery lifetime. Third, a switchless dual-band matching structure is proposed, and the effectiveness of dual-band matching is demonstrated with a fully-integrated CMOS PA. Lastly, a reconfigurable CMOS PA with an automatic antenna mismatch recovery system is presented, which can maintain its original designed performance even under various antenna mismatch conditions. Conclusively, the research in this dissertation provides various solutions for new challenges of advanced mobile terminals.

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

Recent advancements in silicon technology have paved the way for the development of integrated transceivers operating well inside the mm-wave frequency range (30 - 300 GHz). This band offers opportunities for new applications such as remote sensing, short range radar, active imaging and multi-Gb/s radios. This thesis presents new ideas at the circuit and system level for a variety of such applications, up to 145 GHz and in both state-of-the-art nanoscale CMOS and SiGe BiCMOS technologies. After reviewing the theory of operation behind linear and power amplifiers, a purely digital, scalable solution for power amplification that takes advantage of the significant ft/fmax improvement in pFETs as a result of strain engineering in nanoscale CMOS is presented. The proposed Class-D power amplifier, features a stacked, cascode CMOS inverter output stage, which facilitates high voltage operation while employing only thin-oxide devices in a 45 nm SOI CMOS process. Next, a single-chip, 70-80 GHz wireless transceiver for last-mile point-to-point links is described. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gbps. The high bitrate is accomplished by taking advantage of the ample bandwidth available at the W-band frequency range, as well as by employing a direct QPSK modulator, which eliminates the need for separate upconversion and power amplification. Lastly, the system and circuit level implementation of a mm-wave precision distance and velocity sensor at 122 and 145 GHz is presented. Both systems feature a heterodyne architecture to mitigate the receiver 1/f noise, as well as self-test and calibration capabilities along with simple packaging techniques to reduce the overall system cost.