The objective of this research work is to investigate, design and measurement of a digital predistortion linearizer that is able to compensate the dynamic nonlinear distortion of a High Power Amplifier (PA). The effectiveness of the proposed baseband predistorter (PD) on the performance of a WLAN OFDM transmitter utilizing a nonlinear PA with memory effect is observed and discussed. For this purpose, a 10W Class-A/B power amplifier with a gain of 22 dB, operated over the 3.5 GHz frequency band was designed and implemented. The proposed baseband PD is independent of the operating RF frequency and can be used in multiband applications. Its operation is based on the Hammerstein system, taking into account PA memory effect compensation, and demonstrates a noticeable improvement compared to memoryless predistorters. Different types of modelling procedures and linearizers were introduced and investigated, in which accurate behavioural models of Radio Frequency (RF) PAs exhibiting linear and nonlinear memory effects were presented and considered, based on the Wiener approach employing a linear parametric estimation technique. Three new linear methods of parameter estimation were investigated, with the aim of reducing the complexity of the required filtering process in linear memory compensation. Moreover, an improved wiener model is represented to include the nonlinear memory effect in the system. The validity of the PA modelling approaches and predistortion techniques for compensation of nonlinearities of a PA were verified by several tests and measurements. The approaches presented, based on the Wiener system, have the capacity to deal with the existing trade-off between accuracy and convergence speed compared to more computationally complex behavioural modelling algorithms considering memory effects, such as those based on Volterra series and Neural Networks. In addition, nonlinear and linear crosstalks introduced by the power amplifier nonlinear behaviour and antennas mutual coupling due to the compact size of a MIMO OFDM transmitter have been investigated.

This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.

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Modern wireless communication techniques employed in the Wi-Fi® protocol, such as orthogonal frequency-division multiplexing exhibit analogue signals with high peak-to-average power ratio. Therefore, power amplifiers for Wi-Fi suffer from low efficiency when operating in back-off mode, away from their maximum efficiency at peak power. In recent years, digital power amplifiers have been developed to replace their analogue equivalent, taking advantage of easier scaling and circumventing transition frequency issues. Since the digital power amplifier technology for Wi-Fi application is recent, it has not yet replaced robust analogue amplifiers in industrial context. This work proposes to investigate the feasibility and complexity to replace an analogue amplifier with its digital counterpart, with at least the same specification. Among several possible architectures, the reverse class D is chosen for its apparent simplicity. It achieves low power loss into transistors parasitics by operating in square-current mode instead of voltage mode, hence displaying a current-based RF-DAC behaviour. After elaborating the core design with simple efficiency enhancement techniques specific to reverse class D, the layout of the circuitry has been designed. Post-layout simulations have shown the reverse class D digital amplifier designed in CMOS 22nm achieves the required specification of 18dBm average output power with -28dB error vector magnitude in the 2.4GHz range. This basic architecture achieves 19% average drain efficiency, a small improvement over its analogue equivalent currently in use. / Moderna trådlösa kommunikationstekniker som används i Wi-Fi®-protokollet, till exempel ortogonal frekvensdelningsmultiplexering, uppvisar analoga signaler med hög variation i amplitud. Därför har effektförstärkare för Wi-Fi låg verkningsgrad eftersom de arbetar i back-off-läge, långt ifrån sin maximala verkningsgrad vid hög uteffekt. Under de senaste åren har digitala effektförstärkare utvecklats för att byta ut deras analoga motsvarigheter. Eftersom digitala effektförstärkare för Wi-Fi är nya, har de ännu inte ersatt robusta analoga förstärkare i industriella sammanhang. I detta arbete föreslås en undersökning av genomförbarheten och komplexiteten i att ersätta en analog förstärkare med dess digitala motsvarighet, med åtminstone samma specifikation. Bland flera möjliga arkitekturer har den strömbaserade klass D valts på grund av sin enkelhet. Den uppnår låg effektförlust i transistorparasiter genom att arbeta i strömsläge istället för i spänningsläge, och fungerar som en strömbaserade RF-DAC. Efter att ha utarbetat kärnkonstruktionen med enkla tekniker för effektivitetsförbättring som är specifika för strömbaserade klass D har kretsens layout utformats. Simuleringar efter layouten har visat att den digitala förstärkaren i strömbaserade klass D som konstruerats i CMOS 22nm uppnår den nödvändiga specifikationen på 18 dBm genomsnittlig uteffekt med -28 dB felvektorstorlek vid 2,4 GHz. Denna arkitektur uppnår en genomsnittlig verkningsgrad på 19%, vilket är en liten förbättring jämfört med den analoga motsvarighet som för nuvarande används.

Power amplifiers (PAs) convert energy from DC to high frequencies in all radio and microwave transmitter systems be they wireless base stations, handsets, radars, heaters, and so on. PAs are the dominant consumers of energy in these systems and, therefore, the dominant sources of system cost and inefficiency. Research has focused on efficient solid-state PA circuit topologies and their optimization since the 1960s. The 2000s saw the current-mode class-D (CMCD) topology, potentially suitable for today's wireless communications systems, show promise in the UHF frequency band. This thesis describes the design and testing of a high-efficiency CMCD amplifier with an integrated driver stage. In addition, analysis of a merged PA-mixer circuit based on the CMCD is provided.

This works demonstrates the feasibility of the inverse-Class-F harmonic tuning approach for mm-wave silicon PAs. This research addresses the challenges and limitations of the high efficiency inverse-Class-F PAs for mm-wave silicon technology. This work proposes different load networks to mitigate the challenges which are verified with implementations at different mm-wave frequencies with the highest power efficiency performances reported so far: PAE= 50% @ 24 GHz, PAE = 43% @ 41 GHz, and PAE = 23% @ 94 GHz. The design methodology and detailed analysis of the proposed load networks presented and verified with implementation and measured results. / Ph. D.

This letter presents the design and characterization results of a multi-octave power amplifier fabricated in a 0.13μm SiGe-BiCMOS technology. The single stage power amplifier is implemented as the stack of a cascode amplifier combining broadband input matching network with resistive feedback, and a common-base amplifier with base capacitive feedback. Measurement results show that the design delivers a peak saturated output power level of 20.2 dBm, with output 1 dB compression at 19.4 dBm. The measured 3 dB power bandwidth is from 4 GHz to 32 GHz, covering three octaves. The corresponding power fractional bandwidth is 156 %. The measured peak power added efficiency is 20.6 %, and peak small signal gain is 18.6 dB. The fabricated integrated circuit occupies an area of 0.71mm2. To compare state-of-the-art multi-octave power amplifiers, the power amplifier figure of merit defined by the international technology roadmap for semiconductors is modified to include power fractional bandwidth and area. To the knowledge of the authors, the presented design achieves the highest figure of merit among multi-octave power amplifiers in a silicon based integrated circuit technology reported in literature.

Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateur. / This work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier.

This master's thesis deals with design of D class audio final amplifier, which was output power 400 W for 4 ? load impedance. Designed audio amplifier is specifical for active speaker, which consists of satelite speakers and subwoofer. Further more it deals also with other functional blocks, e.g. balanced input preamplifier, active crossover and protection for safety running. Outcome of this work are schemes of each functional blocks of D class audio amplifier, whose functionality was verified by simulation. Thesis also contains full reference material including mechanical arrangement of functional blocks on printed connection board. The conclusion contains the measured parameters of function blocks of produced prototype and complete photographic documentation.

Ce travail s’inscrit dans un projet consistant à développer un prototype de capteur RF autonome et intelligent permettant la réalisation d’un réseau de capteurs sans fil dans un environnement industriel. Cette thèse traite de l’étude, la conception et la réalisation de la partie radiofréquence de la chaîne d’émission sans fils du capteur RF dans la bande ISM 863-870 MHz en technologie CMOS AMS 0.35µm. Cette chaîne inclut toutes les fonctions depuis l’oscillateur local jusqu’à l’amplificateur de puissance. L’émetteur occupe une surface de 0.22mm² et consomme environ 27mA sous une tension d’alimentation de 3.3V. De nombreux principes innovants ont été mis en œuvre et validés. Tous ces principes peuvent être facilement transposés à d’autres standards de communication et dans d’autres bandes de fréquences. Les résultats de simulations du dessin des masques vérifient complètement les spécifications et confirment les simulations. Une caractérisation expérimentale partielle valide les nouvelles architectures proposées. / This work joins in a project consisting in developing prototype of an autonomous and smart RF sensor allowing the realization of a wireless sensor network in an industrial environment. This thesis deals with the study, the design and the realization of the radio-frequency part of the transmitter using the 863-870 MHz ISM band and the CMOS AMS 0.35µm technology. This transmitter includes all the functions from the local oscillator to the power amplifier. The integrated circuit occupies a surface of 0.22mm² and consumes approximately 27mA under a supply voltage of 3.3V. Numerous innovative principles were implemented and validated. All these principles can be easily transposed into other standards of communication and in other frequency bands. The results of the post-layout simulation completely satisfy the specifications and confirm the simulations. Partial experimental characterization validates new architectures proposed.