Cette thèse de doctorat a été réalisée au sein du III-VLab, en partenariat avec l’Institut d’Electronique du Sud (IES). L’objectif de ce travail de thèse vise d’une part à l’optimisation des performances des diodes laser DFB émettant à 780 nm et le développement d’une source plus compacte (MOPA) à 780nm, intégrant de façon monolithique l’oscillateur maître (laser à rétro-action répartie ou DFB) et l’amplificateur de puissance, et d’autre part, à appréhender les phénomènes de bruit, permettant d’évaluer la qualité technologique des lasers. Les développements autour de la longueur d’onde 780 nm, se sont organisés en plusieurs thématiques : les lasers Fabry-Perot et DFB, les amplificateurs (SOA), les MOPA et l’étude du bruit des lasers. Nous avons étudié des structures de différentes épaisseurs de puits quantiques (160Å, 135 Å et 145 Å). La comparaison des performances globales des différentes structures de lasers larges, loin d’être évidente, nous a permis de choisir celle intégrant un puits quantique de 160 Å, pour la réalisation des lasers Fabry-Perot à ruban étroit (3µm à 4µm). Nous avons obtenu sur des lasers larges, de 3 mm de long, bruts de clivage, une puissance d’environ 5 watts par face pour un courant d’injection continu autour de 10 A. Les simulations et caractérisations électro-optiques menées sur des lasers ridge Fabry-Perot, ont servi à affiner le dessin des DFB à 780 nm, par rapport aux briques de base existantes du III-V Lab, et à proposer des structures à cavités optiques larges et super-large (LOC et SLOC) optimisées, en termes de puissance, qualités de faisceau et spectrale.Les mesures de bruits, appuyées d’un modèle de bruit électrique, ont permis d’extraire une valeur du paramètre de Hooge de 2,1.10^-3 pour les lasers ridge, en accord avec la littérature, et qui correspond à une bonne qualité de matériau et technologique des lasers. Différents types d’amplificateurs optiques évasés ont été dessinés, réalisés et caractérisés. Les caractérisations des diverses géométries de SOA, ont donné dans l’ensemble, des valeurs de gain comprises entre 19dB et 25dB. Nous avons obtenu respectivement pour les structures d’amplificateurs à guidages entièrement par l’indice (GI), entièrement par le gain (GG) et mixte (GM), des puissances de 500mW, 750mW et 1W. L’ensemble des résultats obtenus avec ces structures sont prometteurs pour l’intégration monolithique avec le DFB. En ce qui concerne le MOPA, trois approches ont été étudiées: MOPA droit, DFB et amplificateur tiltés de 7° (par rapport à la normale aux faces clivées), et la plus prometteuse mais plus complexe, intégrant le DFB droit et l’amplificateur tilté de 7°, avec une section courbe entre les deux. La prise en compte de l’ensemble des résultats lasers Fabry-Perot, DFB et des résultats d’amplificateurs, nous ont permis de proposer des dessins MOPA originaux. Le dessin du masque réalisé, intègre toutes ces configurations de MOPA, et en plus, des SOA et DFB, qui seront utilisés comme témoins de test lors des caractérisations. / This thesis has been realized in III-VLab in collaboration with the South Electronic Institute in Montpellier. The aim of this work focuses in one hand, on the performance improvement of DFB's diode lasers emitting at 780 nm, and the advanced design of a compact semiconductor laser diode (Master Oscillator Power Amplifier), integrating monolithically the master oscillator (DFB for Distributed Feedback laser); in the other hand, using the noise phenomenon’s studies as a tool, for validating of our laser technologies. The Developments round the 780 nm wavelength, have been divided into different thematic: Fabry-Perot and DFB, Semiconductor Optical Amplifiers (SOA), MOPA, and the lasers noise’s study. We have studied structures with different quantum well thickness (160Å, 135 Å and 145 Å). The comparison of global performances of broad area lasers from these different structures, far to being obvious, allowed us to choose the one that integrates the 160-Å-thickness of quantum-well, for the realization of ridge Fabry-Perot lasers of 3 to 4-µm-of width. We obtained with broad area lasers, as cleaved, with 3-mm cavity lengths, an output power around 5 watts per facet, in continuous bias current around 10 AModellings and electro-optics characterizations performed on ridge Fabry-Perot lasers, allowed to refine DFB lasers at 780 nm, in comparison of the existing building blocks in the lab; we proposed new optimized structures with Large and Super Large Optical Cavities(LOC and SLOC), in terms of optical output power, beam and spectral qualities.The noise measurements with electrical noise modelling, allowed us to extract a value of Hooge’s parameter of 2,1.10^-3, quite in agreement with literature for such lasers, which corresponds to a good material quality and laser technology.Different types of flared SOA have been designed, realized and characterized. The characterizations of various SOA geometries, have given in general, values of gain between 19 dB to 25 dB. With SOAs of types: fully Index Guiding (IG), fully Gain Guiding (GG) and Mixed Guiding (MG), we have respectively obtained 500 mW, 750 mW and 1 W. All the results obtained with these structures are promising for monolithic integration with DFB. Regarding the MOPA, three approaches have been studied. The straight MOPA, the approach of SOA and DFB with 7° tilt(relative to the normal to cleaved facets), and the most complex, but promising approach, integrating the SOA with 7° tilt, and straight DFB, with a bend section between them. By taking into account all the results obtained on Fabry-Perot lasers, DFB, and SOA results, we were able to propose original MOPA designs. The layout drawing has been realized, all the MOPA configurations and additional, DFB and SOA devices, have been included on it. They will be used as test structures for characterizations.

Pour un terminal mobile alimenté sur batterie, le rendement de l’amplificateur de puissance (AP) doit êtreoptimisé. Cette optimisation peut rendre non-linéaire la fonction d’amplification de l’AP. Pour compenser lesdistorsions introduites par le caractère non-linéaire de l’AP, un détecteur numérique fondé sur un modèle deVolterra peut être utilisé. Le comportement de l’AP et le canal étant modélisé par le modèle de Volterra, uneapproche par filtrage de Kalman (FK) permet d’estimer conjointement les noyaux de Volterra et les symbolestransmis. Dans ce travail, nous proposons de traiter cette problématique dans le cadre d’une liaison montantedans un contexte radio intelligente (RI). Dans ce cas, des contraintes supplémentaires doivent être prises encompte. En effet, étant donné que la RI peut changer de bande de fréquence de fonctionnement, les nonlinéaritésde l’AP peuvent varier en fonction du temps. Par conséquent, nous proposons de concevoir une postdistorsionnumérique fondée sur une modélisation par modèles multiples combinant plusieurs estimateurs àbase de FK. Les différents FK permettant de prendre en compte les différentes dynamiques du modèle.Ainsi, les variations temporelles des noyaux de Volterra peuvent être suivies tout en gardant des estimationsprécises lorsque ces noyaux sont statiques. Le cas d’un signal monoporteuse est adressé et validé par desrésultats de simulation. Enfin, la pertinence de l’approche proposée est confirmée par des mesures effectuéessur un AP large bande (300-3000) MHz. / For a battery driven terminal, the power amplifier (PA) efficiency must be optimized. Consequently,non-linearities may appear at the PA output in the transmission chain. To compensatethese distortions, one solution consists in using a digital post-distorter based on aVolterra model of both the PA and the channel and a Kalman filter (KF) based algorithm tojointly estimate the Volterra kernels and the transmitted symbols. Here, we suggest addressingthis issue when dealing with uplink cognitive radio (CR) system. In this case, additionalconstraints must be taken into account. Since the CR terminal may switch from one subbandto another, the PA non-linearities may vary over time. Therefore, we propose to designa digital post-distorter based on an interacting multiple model combining various KF basedestimators using different model parameter dynamics. This makes it possible to track thetime variations of the Volterra kernels while keeping accurate estimates when those parametersare static. Furthermore, the single carrier case is addressed and validated by simulationresults. In addition, the relevance of the proposed approach is confirmed by measurementscarried on a (300-3000) MHz broadband PA.

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.

As wireless communication becomes an ever-more important and pervasive part of our everyday life, system capacity and quality of service issues are becoming more critical. In order to increase the system capacity and improve the quality of service, it is necessary that we pay closer attention to bandwidth and power efficiency issues. Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier modulation technique for high speed data transmission and is generally regarded as bandwidth efficient. However, OFDM signals suffer from high peak-to-average power ratios (PARs) which lead to power inefficiency in the RF portion of the transmitter. Moreover, in OFDM, the well-known pilot tone assisted modulation (PTAM) technique utilizes a number of dedicated training pilots to acquire the channel state information (CSI), resulting in somewhat reduced bandwidth efficiency. In this dissertation, we will address the above mentioned bandwidth and power efficiency issues in wireless transmissions. To avoid bandwidth efficiency loss due to dedicated training, we will first develop a superimposed training framework that can be used to track the frequency selective as well as the Doppler shift characteristics of a channel. Later on, we will propose a generalized superimposed training framework that allows improved channel estimates. To improve the power efficiency, we adopt the selected mapping (SLM) framework to reduce the PARs for both OFDM and forward link Code Division Multiple Access (CDMA). We first propose a dynamic SLM algorithm to greatly reduce the computational requirement of SLM without sacrificing its PAR reducing capability. We propose a number of blind SLM techniques for OFDM and for forward link CDMA; they require no side information and are easy to implement. Our proposed blind SLM technique for OFDM is a novel joint channel estimation and PAR reduction algorithm, for which bandwidth efficiency power efficiency - complexity - bit error rate tradeoffs are carefully considered.

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance.

Digital communication systems which use Orthogonal Frequency Division Multiplexing (OFDM) are now widely used and have many advantages. The main disadvantage is the requirement for highly linear analogue electronics including the high power amplifier (HPA). This requirement cannot be met in all circumstances because of the occurrence of symbols with high peak to average power ratio (PAPR). Such symbols may be non-linearly distorted by limiting. Approaches to solve this problem have been either to reduce the PAPR at the transmitter or to try to mitigate the effect of the non-linearity at the receiver. Soft-limiting, i.e. applying limiting in software prior to the HPA is a simple way to reduce the PAPR. It produces non-linear distortion which will cause an increase in the bit-error-rate (BER) at the receiver. This thesis surveys existing alternatives ways of reducing the effect of non-linearity and proposes some new ones. Two iterative receiver techniques, based on statistical analysis of the nature of the non-linearity, have been implemented and investigated. These are the ‘Bussgang Noise Cancellation’ (BNC) technique and the ‘Decision Aided Reconstruction’ (DAR) techniques. As these techniques are valid for any memory-less nonlinearity, an alternative form of limiting, named as Inverted-Wraparound (IWRAP) has been included in the BNC investigation. A new method is proposed which is capable of correcting the received time-domain samples that are clipped, once they have been identified. This is named the ‘Equation-Method’ and it works by identifying constellation symbols that are likely to be correct at the receiver. If there are a sufficient number of these and they are correctly identified, the FFT may be partitioned to produce a set of equations that may be solved for the clipped time-domain samples. The thesis proposes four enhancements to this new method which improve its effectiveness. It is shown that the best form of this method outperforms conventional techniques especially for severe clipping levels. The performance of these four enhancements is evaluated over channels with additive white Gaussian noise (AWGN) in addition to clipping distortion. A technique based on a ‘margin factor’ is designed to make these methods work more effectively in the presence of AWGN noise. A new combining algorithm referred as ‘HARQ for Clipping’ is presented where soft bit decisions are combined from multiple transmissions. ‘HARQ for Clipping’ has been combined with the best version of the Equation-Method, and the performance of this approach is evaluated in terms of the BER with different levels of AWGN. It has been compared to other approaches from the literature and was found to out-perform the BNC iterative receiver by 3dB at signal to noise ratios around 10dB. Without HARQ, the best version of the Equation-Method performs better than the BNC receiver, at signal-to-nose ratios above about 17dB.

L’objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l’impact de l’évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu’un état de l’art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d’unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond’amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l’apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d’électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d’antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l’impact de ce type de lignes sur les performances des front-end millimétriques. / The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.

This thesis describes the analysis, design and implementation of a high performance DSP-based servo drive for a limited-angle torque motor used in thermal imaging applications. A limited-angle torque motor is an electromagnetic actuator based on the Laws' relay principle, and in the present application the rotation required was from - 10° to + 10° in 16 ms, with a flyback period of 4 ms. To ensure good quality picture reproduction, an exceptionally high linearity of ±0.02 ° was necessary throughout the forward sweep. In addition, the drive voltage to the exciting winding of the motor should be less than the +35 V ceiling of the drive amplifier. A research survey shows that little literature was available, probably due to the commercial sensitivity of many of the applications for torque motors. A detailed mathematical model of the motor drive, including high-order linear dynamics and the significant nonlinear characteristics, was developed to provide an insight into the overall system behaviour. The proposed control scheme uses a multicompensator, multi-loop linear controller, to reshape substantially the motor response characteristic, with a non-linear adaptive gain-scheduled controller to compensate effectively for the nonlinear variations of the motor parameters. The scheme demonstrates that a demanding nonlinear control system may be conveniently analysed and synthesised using frequency-domain methods, and that the design techniques may be reliably applied to similar electro-mechanical systems required to track a repetitive waveform. A prototype drive system was designed, constructed and tested during the course of the research. The drive system comprises a DSP-based digital controller, a linear power amplifier and the feedback signal conditioning circuit necessary for the closed-loop control. A switch-mode amplifier was also built, evaluated and compared with the linear amplifier. It was shown that the overall performance of the linear amplifier was superior to that of the switch-mode amplifier for the present application. The control software was developed using the structured programming method, with the continuous controller converted to digital form using the bilinear transform. The 6- operator was used rather than the z-operator, since it is more advantageous for high speed sampling systems. The gain-scheduled control was implemented by developing a schedule table, which is controlled by the DSP program to update continuously the controller parameters in synchronism with the periodic scanning of the motor. The experimental results show excellent agreement with the simulated results, with linearity of ±0.05 ° achieved throughout the forward sweep. Although this did not quite meet the very demanding specifications due to the limitations of the experimental drive system, it clearly demonstrates the effectiveness of the proposed control scheme. The discrepancies between simulated and experimental results are analyzed and discussed, the control design method is reviewed, and detailed suggestions are presented for further work which may improve the drive performance.

L’essor et l’évolution des systèmes de télécommunication sont liés inéluctablement à la montée en fréquence et à l’augmentation des bandes passantes des futurs systèmes d’une part, et à une place sans cesse croissante prise par l’électronique numérique dans les chaînes d’émission/réception d’autre part. Concernant ce deuxième aspect, la génération de puissance RF avant émission est encore à ce jour implémentée de façon analogique, mais la gestion énergétique des amplificateurs de puissance RF est de plus en plus assistée numériquement. L’apparition du ‘numérique’ dans le domaine de la puissance RF se traduit par la mise en œuvre de systèmes électroniques fonctionnant en commutation : modulateurs de polarisation pour l’envelope tracking, convertisseurs numérique-analogique de puissance (Power-DAC) ou amplificateurs en commutation à fort rendement (classe S ou D). C’est dans ce contexte que s’inscrivent ces travaux de thèse : deux dispositifs de commutation originaux à base de transistors GaN HEMT sont présentés, analysés et réalisés en technologie MMIC. Ces cellules de commutation élémentaires permettent, jusqu’à des fréquences de quelques centaines de MHz, de commuter des tensions jusqu’à 50V, avec des puissances de l’ordre de 100W, ceci avec un rendement énergétique supérieur à 80%. Ces cellules de commutation sont ensuite utilisées dans diverses applications : deux types de modulateurs de polarisation destinés à l’envelope tracking ainsi que deux architectures d’amplificateurs classe D (demi-pont et pont en H) sont étudiés et les résultats expérimentaux permettent de valider ces différentes topologies. / Telecommunication systems development is linked to working frequency and bandwidths increasement of future systems on one hand, and the growing place taken by digital electronics in the transmission chains on the other hand. Concerning the second point, the RF power generation in emitters is still implemented in an analog way, but the energy management of the RF power amplifiers is more and more assisted by numeric devices. The appearance of the 'digital technology' in the field of RF power is characterized by the implementation of high speed switching electronic systems like bias modulators for envelope tracking, power digital to analog converters (Power-DAC) or switching mode RF amplifiers (Classe S or D). This thesis work fits in this context, it describes two original switching devices based on GaN HEMT transistors. These elementary switching cells are realized in MMIC technology, they allow switching frequencies up to few hundreds MHz, with voltages reaching 50V, powers about 100W and energy efficiency greater than 80%. These switching cells are then used in various applications: two kinds of bias modulators for envelope tracking system as well as two architectures of class D amplifiers (half-bridge and full-bridge) are analyzed and validated by experimental results.

Software Defined Radios (SDRs) and Cognitive Radios (CRs) pave the way for next-generation radio technology. They promise versatility, flexibility and cognition which can revolutionize communications systems. However they present greater challenges to the design of radio frequency (RF) front-ends. RF front-ends for the radios in use today are narrow-band in their frequency response and are optimized and tuned to the carrier frequency of interest. SDRs and CRs demand front-ends which are versatile, configurable, tunable and be capable of transmitting and receiving signals with different bandwidths and modulation schemes. Integrating power amplifiers (PAs) with transmitters in CMOS has many advantages and challenges. This thesis deals with the design of an RF transmitter front-end for SDRs and CRs in CMOS. The thesis begins with an introduction to SDRs and the requirements they place on transmitters and the challenges involved in designing them in CMOS. After a brief overview of the existing techniques, the proposed architecture is presented and explained. A digitally intensive transmitter solution is proposed. The transmitter covers a wide frequency range of 750 MHz to 2.5 GHz. The inputs to the proposed transmitter are in-phase and quadrature (I & Q) data bit streams. Multiple stages of up-sampling and filtering are used to remove all spurs in the spectrum such that only the harmonics of the carrier remain. Differential rail-to-rail quadrature clocks are generated from a continuous wave signal at twice the carrier frequency. The clocks are corrected for their duty cycle and quadrature impairments. The heart of the transmitter is an integrated reconfigurable CMOS power amplifier (PA). A methodology to design reconfigurable Class E PAs with a series fixed inductor has been presented. A CMOS power amplifier that can span a wide frequency range with sufficient output power and efficiency, supporting varying envelope complex modulation signals, with good linearity has been designed. Digital pre-distortion (DPD) is used to linearize the PA. The full transmitter and the clock correction blocks have been designed and fabricated in a commercial 130-nm CMOS process and experimentally characterized. The PA delivers a maximum power of 13 dBm with an efficiency of 27% at 1 GHz. While transmitting a 16-QAM signal at 1 GHz, the measured EVM is 4%. It delivers a maximum power of around 11-13 dBm from 750 MHz to 1.5 GHz and up to 6.5 dBm of power till 2.5 GHz. Comparing the proposed system with recently published literature, it can be seen that the proposed design is one of the very few transmitters which has an integrated matching network, tunable across the frequency range. The proposed PA produces the highest output power and with largest efficiency for systems with on-chip output networks.