La variation de vitesse des machines électriques est une application très porteuse de l’électronique de puissance. La solution de conversion la plus répandue consiste à connecter en cascade deux convertisseurs statiques et d’effectuer une double conversion (AC/DC/AC). Une autre solution, faiblement répandue dans l’industrie, effectue une conversion directe AC/AC. Ce mémoire effectue une synthèse sur les solutions de conversion directe ainsi que sur les stratégies de modulation des convertisseurs matriciels et matriciels « double étage » dans le but de piloter des machines électriques triphasées à partir d’un réseau alternatif triphasé. Cette synthèse a permis de développer une modulation scalaire généralisée, associée à un modulateur par porteuse, équivalente à la modulation vectorielle et applicable aux différents convertisseurs matriciels. Les modulations, à nombre de commutation réduit par période de découpage, ont été approfondies. Cette généralisation a permis de mettre en évidence une solution réduisant les pertes et améliorant le comportement électromagnétique du dispositif comparativement aux modulations traditionnellement utilisées. La présentation des contraintes réelles (commande rapprochée des interrupteurs, Les protections ainsi que le filtrage) est abordée et a été utilisée pour développer une maquette laboratoire. Les stratégies de modulation ont été implantées expérimentalement et valident l’étude théorique. Enfin, un fonctionnement direct à la fréquence réseau, sans modulation donc à faibles pertes, est proposé. Un fonctionnement particulier est introduit, permettant d’effectuer le transitoire du mode modulé classique au fonctionnement direct non modulé / In the power electronics field, the adjustable speed drives is a growing application for electric motors control. The most common conversion solution is to connect in series two static converters and perform a double conversion (AC/DC/AC). Another solution, hardly proposed by industry, uses a direct AC/AC conversion. This thesis aims to make a direct conversion solutions and matrix converters and ‘‘two stage’’ matrix converters modulation strategies synthesis for the purpose to control three-phase electric motor with a three phase input network. This synthesis has developed a generalized scalar modulation, combined with a carrier wave modulator, equivalent to the space vector modulation and applied to matrix converters and the ‘‘two stage’’ matrix converters. Some attention has been done to reduced the switching number during the modulation period. The generalization allows to propose a modified modulation which reduces the losses and improves the electromagnetic performance compared to the traditional modulations used for these kind of converters. The practical constraint (switches control, protection system and filtering) are discussed and has been used to develop a laboratory prototype. The modulations strategies have been implemented experimentally and validate the theoretical study. Finally, a direct function mode with an equal frequency between the input and output network is proposed, without modulation and therefore low losses. In the last part, a particular operation mode is then introduced, permitting the transient operation between the modulated conventional mode to the direct mode without modulation

Submitted by Gilvanedja Silva (gilvanedja@biblioteca.ufpb.br) on 2018-03-22T20:42:08Z No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) / Made available in DSpace on 2018-03-22T20:42:09Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) Previous issue date: 2017-05-25 / This work presents a technique using carrier-based pulse width modulation (PWM) applied to single-phase asymmetrical multilevel inverters with diodes clamped, aiming to increase the amount of output voltage levels to improve signal quality, reducing the total harmonic distortion rate (THD). The technique was used in inverters of three, four and five levels per arm, providing an output signal with seven, thirteen and nineteen levels respectively, presenting two, six and ten levels higher than the equivalent symmetrical multilevel inverters. The technique was described with a set of equations and procedures that can be generalized for inverters of any number of levels. To verify the operation, simulations were performed using the PSIM program and an experimental assembly of an asymmetrical multilevel inverter of three levels was performed, using a field programmable gate array device (FPGA) in the implementation of the PWM modulator. Finally, the simulation and experimental results that prove the effectiveness of the modulation strategy employed in this work are presented and compared / Este trabalho apresenta uma técnica utilizando a modulação por largura de pulso (PWM) baseada em portadora, aplicada aos inversores multiníveis monofásicos assimétricos com diodos de grampeamento, com o objetivo de elevar a quantidade de níveis na tensão de saída, para melhorar a qualidade do sinal, reduzindo a taxa de distorção harmônica total (THD). A técnica foi empregada em inversores de três, quatro e cinco níveis por braço, fornecendo um sinal de saída com sete, treze e dezenove níveis respectivamente, apresentando dois, seis e dez níveis a mais que os inversores multiníveis simétricos equivalentes. A técnica foi descrita com um conjunto de equações e procedimentos que pode ser generalizada para inversores de qualquer número de níveis. Para comprovar o funcionamento, foram realizadas simulações utilizando o programa PSIM e efetuada montagem experimental de uma inversor multinível assimétrico de três níveis, utilizando na implementação do modulador PWM um dispositivo em matriz de porta programável em campo (FPGA). Por fim, são apresentados e comparados os resultados de simulações e experimentais que comprovam a eficácia da estratégia de modulação empregada neste trabalho

Voltage source inverter (VSI) fed induction motors are increasingly used in industrial and transportation applications as variable speed drives. However, VSIs generate non-sinusoidal voltages and hence result in harmonic distortion in motor current, motor heating, torque pulsations and increased acoustic noise. Most of these undesirable effects can be reduced by increasing the switching frequency of the inverter. This is not necessarily true for acoustic noise. Acoustic noise does not decrease monotonically with increase in switching frequency since the noise emitted depends on the proximity of harmonic frequencies to the motor resonant frequencies. Also there are practical limitations on the inverter switching frequency on account of device rating and losses. The switching frequency of many inverters often falls in the range 2 kHz - 6 kHz where the human ear is highly sensitive. Hence, the acoustic noise emission from the motor drive is of utmost important. Further, the acoustic noise emitted by the motor drive is known to depend on the waveform quality of the voltage applied. Hence, the acoustic performance varies with the pulse width modulation (PWM) technique used to modulate the inverter, even at the same modulation index. Therefore a comprehensive study on the acoustic noise aspects of induction motor drive is required. The acoustic noise study of the motor drive poses multifaceted challenges. A simple motor model is sufficient for calculation of total harmonic distortion (THD). A more detailed model is required for torque pulsation studies. But the motor acoustic noise is affected by many other factors such as stator winding distribution, space harmonics, geometry of stator and rotor slots, motor irregularities, structural issues controlling the resonant frequency and environmental factors. Hence an accurate model for acoustic noise would have to be very detailed and would span different domains such as electromagnetic fields, structural engineering, vibration and acoustics. Motor designers employ such detailed models along with details of the materials used and geometry to predict the acoustic noise that would be emitted by a motor and also to design a low-noise motor. However such detailed motor model for acoustic noise purposes and the necessary material and constructional details of the motor are usually not available to the user. Also, certain factors influencing the acoustic noise change due to wear and tear during the operational life of the motor. Hence this thesis takes up an experimental approach to study the acoustic noise performance of an inverter-fed induction motor at any stage of its operating life. A 10 kVA insulated gate bipolar transistor (IGBT) based inverter is built to feed the induction motor; a 6 kW and 2.3 kW induction motors are used as experimental motors. A low-cost acoustic noise measurement system is also developed as per relevant standards for measurement and spectral analysis of the acoustic noise emitted. For each PWM scheme, the current and acoustic noise measurements are carried out extensively at different carrier frequencies over a range of fundamental frequencies. The main cause of acoustic noise of electromagnetic origin is the stator core vibration, which is caused by the interaction of air-gap fluxes produced by fundamental current and harmonic currents. In this thesis, an experimental procedure is suggested for the acoustic noise characterization of an induction motor inclusive of determination of resonant frequencies. Further, based on current and acoustic noise measurements, a vibration model is proposed for the stator structure. This model is used to predict the acoustic noise pertaining to time harmonic currents with reasonable accuracy. Literature on motor acoustic noise mainly focuses on sinusoidal PWM (SPWM), conventional space vector PWM (CSVPWM) and random PWM (RPWM). In this thesis, acoustic noise pertaining to two bus-clamping PWM (BCPWM) schemes and an advanced bus-clamping PWM (ABCPWM) scheme is investigated. BCPWM schemes are mainly used to reduce the switching loss of the inverter by clamping any of the three phases to DC rail for 120◦ duration of the fundamental cycle. Experimental results show that these BCPWM schemes reduce the amplitude of the tonal component of noise at the carrier frequency, compared to CSVPWM. Experimental results with ABCPWM show that the overall acoustic noise produced by the motor drive is reduced at low and medium speeds if the switching frequency is above 3 kHz. Certain spread in the frequency spectrum of noise is also seen with both BCPWM and ABCPWM. To spread the acoustic noise spectrum further, many variable-frequency PWM schemes have been suggested by researchers. But these schemes, by and large, increase the current total harmonic distortion (THD) compared to CSVPWM. Thus, a novel variable-frequency PWM (VFPWM) method is proposed, which offers reduced current THD in addition to uniformly spread noise spectrum. Experimental results also show spread in the acoustic noise spectrum and reduction in the dominant noise components with the proposed VFPWM. Also, the current THD is reduced at high speeds of the motor drive with the proposed method.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

This master´s thesis describes switch mode power supply. The aim of this master´s thesis is the design and the construction of the switch mode power supply, which will be used as a laboratory tool.

This thesis deals with the effect of frequency inverter on the lifetime of roller bearings. The measurement has been carried out on the frequency inverter and induction motor by Siemens in the Switchgear laboratory of Fakulty of elektrical engineering and communication. Data has been recorded and processed on Adash VA4 Pro analyzer. Methods of measuring RMS values and frequency analysis of vibration and current were used for the analysis. Based on the mutual similarity of frequency spectrum, the presence of the high frequency capacitive current in the bearings has been proven. To prevent this, possible solutions have been presented. In the second part of the experiment an effect of changing pulse width modulation (PWM) on vibration was examined. The goal was to make a basic analysis and to provide background material for further research.

Master thesis deals with design controllable switching power source. Device is supplied and controlled via USB bus of PC. The required output parameters are specified by user in a computer application. The teoretical part includes method of USB communication and introduction to switching power sources with focus on a Sepic topologii. The practical part describe individual circuit solution which contains of a complete device. Is analyzed in detail the proposal Sepic converter circuit and controling by microcontroller. The work also includes the design of microcontroller and computer applications. The result of this thesis is a functional device on which is the performed measurement.

Hlavným cieľom tejto práce je vytvorenie simulácií rôznych algoritmov riadenia asynchrónneho motora a vzájomné porovnanie ich vlastností. Zaoberá sa taktiež možnosťami konfigurácie náhradného zapojenia na T-článok, -článok a -článok. Obsahuje jednak teoretický rozbor, a taktiež aj simulácie jednotlivých spôsobov riadenia spolu s podrobným návodom na ich realizáciu. Celkovo budú vykonané 3 simulácie – simulácia vektorového riadenia s orientáciou na rotorový tok, vektorového riadenia s orientáciou na statorový tok a simulácia takzvaného prirodzeného riadenia. Ide o úplne nový typ riadenia, ktorého autorom je vedúci tejto diplomovej práce. Jeho simulácia bola vôbec prvým pokusom o funkčnú realizáciu tohto typu riadenia.

In power electronics, the switched converter plays a fundamental role in the efficient conversion and dynamical control of electrical energy. Due to the switching operation of these systems, overlaid disturbances come into existence in addition to the desired behavior of the variables, causing deviations in the current and voltages. From a control perspective, these disturbances are of no interest since they cannot be compensated. They can even alter the measurements given to the control system, affecting its behavior. Furthermore, during the control design, averaged models are often used, by which the switching operation is somehow disregarded. They consider instead the average behavior of the system variables. Thus, it is essential that the measuring setup provides a measurement of the average value to the control system. To accomplish this goal, there are in practice different approaches. For example, the disturbances originated by the switching operation can be either suppressed using an analog or digital filter, or the sampling of the variables can be carried out in a suitable manner, synchronous to the carrier of the modulation method. Unfortunately, the use of filters adds an extra phase shift or delay to the control loop, reducing its dynamical performance. Moreover, the synchronous sampling method provides a good approximation of the average value only if certain conditions are met, otherwise a distortion due to aliasing takes place. A method is developed in this work to predict, in every switching cycle, the average value of the system variables in a switched power converter. In this context, the work presents an alternative method to carry out the measurement of the average value, avoiding the principal drawbacks of the standard measuring methods. To achieve this, a suitable model of the converter is used, incorporating the modulation method and the type of analog-to-digital converter, either a conventional sample-and-hold or a sigma-delta converter. The measurement given by the analog-to-digital converter is used to predict the time behavior of the system variables during the present switching period and then to evaluate its average value, before the period is completed. The method allows to obtain simultaneously the average value of currents and voltages, to get rid of the delay introduced by filtering, and to avoid the drawback of sampling in the measurement, i.e. aliasing. In this work, an overview of the standard measuring methods for switched power converters is first presented. The problematics that arise from the sampling process are also discussed. Next, the theoretical grounds of the method are developed and the tools needed to implement it are derived. To illustrate its applicability, the method is used first in DC-DC converters, where the case of the buck converter is analyzed in detail. Similarly, the method is applied to a three-phase two-level voltage source converter. In both cases, simulation results and experimental verification are presented for different operational modes. The usage of the method in open and closed loop is discussed, and its effect in the system behavior is shown. The performance of the prediction method is contrasted with other standard measuring methods.

<p>To facilitate indoor air quality (IAQ) monitoring, the research described herein develops and implements methods for the electronic integration of two types of gas sensor, each functionalized with a polymer blend tailored for CO₂ detection. A highly sensitive and tunable electronic chemiresistive sensor interface was developed and experimentally validated. This device achieved analog-to-digital conversion (ADC) through a pulse width modulated (PWM) signal, temporary data storage with an efficient data buffering system, and noise reduction and signal amplification utilizing an instrumentation amplifier integrator circuit. These techniques can used beyond CO₂-specific applications to compensate for certain undesirable chemiresistive sensor characteristics, such as low response magnitude and signal noise. Additionally, resonant mass sensing circuitry was combined with an on-chip field programmable gate array (FPGA) implemented frequency counter. Hz-level resolution was achieved with an Alorium Snō FPGA board and a Verilog data acquisition and communication program. This device can monitor up to 16 sensor channels simultaneously and has a straightforward interface with a controllable output. Furthermore, the functionality of each integrated sensor was experimentally validated. With additional work, these integrated designs have the potential to be inexpensive, low-power, highly sensitive devices that are suitable for practical use in IAQ monitoring applications.</p>