As the costs of large-scale power generation and transmission rise, distributed generation is becoming a prevalent alternative used by a growing number of both residences and businesses. Distributed generation systems typically consist of two main components: a small-scale, often high-efficiency or renewable power source, such as a fuel cell, solar panel, or wind turbine, and a power electronic converter to convert the raw power produced by the source to a usable form. In North America, the majority of power used in residential and light commercial locations is provided in a form known as single-phase three-wire, or split-phase. This consists of two half-phase AC voltages, each of 110 to 120V rms, and one combined AC voltage of 220 to 240V rms. It is therefore necessary for distributed generation systems to supply power in this same form so that it can be used by standard loads such as lighting or appliances, and the excess power can be fed back into the distribution grid. The most common type of converter used to make this conversion is the voltage-sourced inverter (VSI). There are, however, some advantages to using a current-sourced inverter (CSI) instead. These include improved output voltage waveform quality, built-in voltage boost, and built-in overcurrent protection. However, there are also two obstacles that have prevented the adoption of current-sourced inverters to date. The first obstacle to the use of current-sourced inverters is that they require a DC current input to operate. Therefore, a circuit and control algorithm must be developed to produce a DC current from a low DC voltage source. The first part of this thesis deals with the generation of a suitable DC current. The second major obstacle to adopting current-sourced inverters is that no algorithm for producing single-phase three-wire outputs with a CSI presently exists in literature. The second part of this thesis develops such a switching algorithm, using a three-leg current-sourced inverter. The algorithm is demonstrated using simulation and experimental results, which show that the proposed system is able to successfully generate balanced output voltages under unbalanced loading conditions while equalizing switch utilization and minimizing output voltage ripple.

This thesis is about the improved design of small size brushless DC fan motor driving circuit. Two main improvements in the new design are increase the stability and decrease the size of motor fan at the same time. To improve the stability, there are two major parts added to the original driving circuit. The delay circuit that protects the H-bridge and the output low current limit circuit. Furthermore, it is believed that the speed control also can improve the stability. With regard to the rotation speed control, two circuits are attached to the motor, 1) speed feedback controller and 2) speed and current feedback controller. Both controllers are attached in the close loop rotation speed control circuit. They are used to increase the efficiency of drive circuit. In order to make the circuit more efficient, they solve problems such as disturbance in miscellaneous noise; also the power dissipation that occurs in open loop rotation speed control circuit. The second improvement in the new design is to reduce the cost and size of system. The design of sensorless control scheme is proposed to replace the Hall sensor to detect rotor position. This sensorless scheme can also supply fan motor voltage to achieve the speed control.

A high efficiency driver circuit is proposed for Light Emitting Diode (LED) lamps with dimming feature. The current regulation is accomplished by processing partial power of the power conversion circuit so that a high overall efficiency can be realized. The detailed description and analysis of circuit operation are provided. The dimming feature can be accomplished by means of linear current regulation, pulse-width modulation (PWM) or double pulse-width modulation (DPWM). Based on the circuit analyses and derived equations, a laboratory circuit is designed for an LED lamp which is composed of 40 high-brightness white LEDs in series. The performances with three dimming schemes are compared from the measured results. LEDs dimmed by DPWM have less color shift than those dimmed by linear current regulation and PWM. On the other hand, the dimming scheme with linear current regulation has the highest light efficiency over the entire dimming range. The circuit efficiency can be as high as 95.5% at the rated output and deteriorates slightly to 90.5% as the lamp is dimmed to 10% of the rated power.

This thesis presents a novel modulation scheme, called feedback dithering modulation, for DC to AC power converters. The feedback dithering modulator consists of a quantizer and a recently reported feedback dithering circuit, performing multilevel modulation with improved linearity and signal quality as opposed to the conventional modulation schemes. By combining the feedback dithering modulation and optimal control, a single-phase DC to AC power converter is built and tested. The resulting total harmonic distortion can be as low as 0.38% for a 25£[ load, or 0.47% when the output is open. Under the various operating conditions with DC voltages source varying from 190 V to 300 V and output powers from 0 to 600 W, the power converter always maintains a total harmonic distortion less than 1%, exhibiting high performance and excellent robustness.

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load. This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load.

In this dissertation, new high frequency link power conversion systems for the fuel cell power conditioning are proposed to improve the performance and optimize the cost, size, and weight of the power conversion systems. The first study proposes a new soft switching technique for the phase-shift controlled bi-directional dc-dc converter. The described dc-dc converter employs a low profile high frequency transformer and two active full-bridge converters for bidirectional power flow capability. The proposed new soft switching technique guarantees soft switching over wide range from no load to full load without any additional circuit components. The load range for proposed soft switching technique is analyzed by mathematical approach with equivalent circuits and verified by experiments. The second study describes a boost converter cascaded high frequency link direct dc-ac converter suitable for fuel cell power sources. A new multi-loop control for a boost converter to reduce the low frequency input current harmonics drawn from the fuel cell is proposed, and a new PWM technique for the cycloconverter at the secondary to reject the low order harmonics in the output voltages is presented. The performance of the proposed scheme is verified by the various simulations and experiments, and their trade-offs are described in detail using mathematical evaluation approach. The third study proposes a current-fed high frequency link direct dc-ac converter suitable for residential fuel cell power systems. The high frequency full-bridge inverter at the primary generates sinusoidally PWM modulated current pulses with zero current switching (ZCS), and the cycloconverter at the secondary which consists of only two bidirectional switches and output filter capacitors produces sinusoidally modulated 60Hz split single phase output voltage waveforms with near zero current switching. The active harmonic filter connected to the input terminal compensates the low order input current harmonics drawn from the fuel cell without long-term energy storage devices such as batteries and super capacitors.

<p>Denna högskoleavhandling beskriver konstruktionen av ett system vars funktion är att PID-reglera ett linjärställdon kopplad till venturi. Syftet har varit att få fram en reglering på venturin så att förutsättningarna förblir desamma vid mätning av olika temperaturer och lufttryck i en testrigg. Denna testrigg används för att utveckla produkten Varivent som används för att uppfylla högre miljökrav på förbränningsmotorer.</p><p>I arbetet beskriver jag de olika krav som funnits för att bygga det nya systemet, dessa var ingångar, utgångar, mikroprocessor, reglering,</p><p>kommunikation samt övriga krav. Jag diskuterar de svårigheter och möjligheter som är förknippade med kraven och tar även upp de komponenter jag använt samt deras egenskaper. Det svåraste momentet har varit PID-regulatorn som både varit en viktig och en svårlöslig del i konstruktionen av systemet. Slutligen diskuterar jag resultatet där jag, i en analys, kan se att jag kunde underlättat för mig själv med andra angreppsvinklar men att det slutliga resultatet ändå blivit mycket tillfredsställande.</p> / <p>This bachelor thesis describes the design of a unit the function of which is to regulate, using PID controls, a linear mechanical adjusting screw coupled to a variable venturi flow system. The design criteria has been to create, in a test rig, a venturi control system that gives an output that is not affected by changes in either air temperature or pressure. The test rig is used for the development of Varivent, a product used to reduce the environmental impact of the internal combustion engine. In my thesis work I describe the various and necessary elements of the project. These can be termed inputs, outputs, microprocessors, regulators and communicators. I discuss the difficulties and possibilities associated with the design criteria and mention the components used and their different attributes. The most challenging part of the project has been the design of the PID regulator, which, whilst being the heart of the system, has also been the most difficult part of the system to design. Finally I discuss my results where, in an analysis, I see that I could have made things easier for myself had I approached the problems in other ways but that the final result was, despite this, very satisfactory.</p>

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

Η ψηφιακή τεχνολογία έχει διεισδύσει πλήρως στην περιοχή της Ακουστικής και της Τεχνολογίας Ήχου, όπως επίσης και σε όλους σχεδόν τους κλάδους της σύγχρονης επιστήμης και της τεχνολογίας. Στον τομέα των ηλεκτρονικών για ηχητικές εφαρμογές, ιδιαίτερα καθοριστικό ρόλο κατέχουν οι ενι- σχυτές. Σκοπός της εργασίας αυτής, είναι να παρουσιάσει το λειτουργικό μοντέλο ενός ψηφιακού ενι- σχυτή Class-D για ηχητικά σήματα, το οποίο προσομοιώθηκε και λειτούργησε σε περιβάλλον Matlab & Simulink. Στο τέλος παρουσιάζονται τα αποτελέσματα χρήσιμων μετρήσεων για σημαντικούς δεί- κτες της ηλεκτροακουστικής όπως η Απόκριση Συχνότητας, Total Harmonic Distortion(THD), Total Harmonic Distortion plus Noise (THD+N) ως προς τη συχνότητα και ως προς την ισχύ, από όπου βγαίνουν συμπεράσματα σχετικά με την ποιότητα και την απόδοση της συγκεκριμένης τεχνολογίας υλοποίησης. / DigitalTechnology has been fully into Acousctics and Audio Technology,as in virtually all branches of modern science and technology.In audio electronics applications, amplifiers have a significant role. The purpose of this thesis is to present the functional model of a digital Class-D amplifier for audio signals, which has been simulated and run in Matlab & Simulink environment. Finally the results of measurements relating to some important electroacoustics indexes like Frequency Response, Total Harmonic Distortion (THD), Total Harmonic Distortion plus Noise (THD+N), relative to the audio signal’s frequency and power, are presented and lead to some conclusions concerning the quality and efficiency of this implementation technology.