In the current transmission system, the information bandwidth of the optical fiber communication system is limited by optical amplifier bandwidth, and more efficient use of bandwidth is a very important issue. Amplitude and phase shift keying (APSK) is an advanced modulation scheme to improve the spectral efficiency and can effectively increase the transmission capacity. Certainly, APSK format has a good potential for development. This master thesis is focusing on that to study the transmission performance of the APSK format using digital coherent receiver. As the extinction ratio (ER) of the amplitude shift keying (ASK) signal affects the performances of the ASK signal and phase shift keying (PSK) signal simultaneously, the effect of the ER on the APSK transmission performance was studied. The APSK format has the trade-off between the performances of both the ASK signal and the PSK signal through the ER of the ASK signal. To overcome this issue, a method named zero-nulling method had been proposed, and this method solved the trade-off issue properly. At first, the amendment is to modify the digital coherent receiver program, confirmed that the digital coherent receiver program can correctly resolve APSK signal. Second, in this master thesis, I set up a 500km long optical fiber to measure the transmission performance under APSK format, and try to use recirculating loop system to further increase the transmission distance to several thousand kilometers. Finally, by further modify the receiver program to achieve APSK modulation of the zero-nulling method, and can prove its feasibility.

Ultra-wideband systems can be used in indoor wireless personal area network (WPAN) or short-range wireless local area network (WLAN) transmission. Yet owing to the effects of indoor dense multipath, it will cause more power consumption. We usually use Rake receiver to improve system performance. However, we should do some compromise between system performance and the design complexity. Thus, the concept of Selective Rake can be used to substitute for the conventional Rake receiver. Selective Rake receiver uses fewer but more powerful paths instead of using all the paths to raise system performance. Hence, we have to precisely detect the multipath components for best performance. Earlier we use CLEAN algorithm to estimate the multipath components. The CLEAN algorithm can be used in selecting the paths with relatively high energy. But as the impact of frequency selective fading makes the transmitted signal distorted, the CLEAN algorithm no longer applies to this situation. Thus, we use Multiscale CLEAN algorithm instead. Multiscale CLEAN algorithm calculate the value of cross-correlation between the received signal and a set of waveforms, and then choose the higher one as the waveform transmitted. Besides, we use Maximal Ratio Combining to weigh the different paths to get the signal with more power. We represent the signal affected by frequency selective fading by using the second derivatives of Gaussian waveform function with different effective widths of pulse. The waveforms corresponding different effective widths have different spectra which represent the different effects of fading. It is seen that that the multiscale CLEAN has better performance than the CLEAN algorithm with more precise estimation of multipath components. In simulation result, we can figure out path searching using Multiscale CLEAN algorithm is more accurate than using CLEAN algorithm. Even the path with smaller energy gain, using multiscale CLEAN algorithm can search successfully, while CLEAN algorithm cannot do.

The first part of this thesis studies the wire-bonding technology for use in an integrated design of transformer balun and RF front-end receiver, which is realized by IPD and CMOS technology, respectively. In this part, the RF front-end receiver and the balun were designed separately, and the bondwire model was established based on electromagnetic simulation. For the maximum power transfer and optimal noise performance, the input impedance between the CMOS RF front-end receiver and the IPD balun was conjugate-matched. The IPD balun, placed in front of the differential LNA of a direct-conversion receiver, is designed using the IPD technology, thereby reducing the insertion loss, and subsequently improving the noise figure of the CMOS receiver. The second part of this thesis uses a vertically coupled transformer balun with a primary coil made by IPD technology and a secondary coil made by CMOS technology. This balun has a low-loss advantage when integrated with a posterior differential LNA. Finally, the magnetic resonance coupling for use in signal transmission is studied and experimented on a printed circuit board.

This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS). A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 £gm CMOS process. In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 £gm 60V HV CMOS process.

A fully-differential base-band transimpedance low-pass filter is designed for use in a direct conversion wireless receiver. Existing base-band transimpedance amplifiers (TIA) often utilize single-pole filters which do not provide good stop-band rejection and may even allow the filter to saturate in the presence of large interferers near the edge of the pass-band. The designed filter is placed in parallel with an existing single-pole TIA filter and diverts stop-band current signals away from the existing filter, providing added rejection and safeguarding the filter from saturating. The presented filter has a bandwidth of 10 MHz, achieves 35 dB rejection at 50 MHz (25 dB in post-layout simulations), and can process interferers as large as 10 mA. The circuit is designed in Jazz 0.18 m CMOS technology, and it is shown, using macromodels, that the design is scalable to smaller, faster technologies.

Ultra-wideband technology (UWB) has received tremendous attention since the FCC license release in 2002, which expedited the research and development of UWB technologies on consumer products. The applications of UWB range from ground penetrating radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process makes the CMOS circuit capable of handling signal at multi-giga herz. However, some design challenges still remain to be solved. Unlike regular narrow band signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results in the occupancy of wide frequency range. This demands that UWB front-end circuits deliver both time domain and frequency domain signal processing over broad bandwidth. Witnessing these technique challenges, this dissertation aims at designing novel, high performance components for UWB signal generation, down-conversion, as well as accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to facilitate the discrete feature of the UWB signal. The transmitter employs novel twostage -switching to generate carrier based UWB signal. The structure not only minimizes the current consumption but also eliminates the use of a UWB power amplifier. The fabricated transmitter is capable of delivering tunable UWB signal over the complete 3.1GHz -10.6GHz UWB band. By applying the similar two-stage switching approach, we were able to implement a novel switched-LNA based UWB sampling receiver frontend. The proposed front-end has significantly lower power consumption compared to previously published design while keep relatively high gain and low noise at the same time. The designed sampling mixer shows unprecedented performance of 9-12dB voltage conversion gain, 16-25dB noise figure, and power consumption of only 21.6mW(with buffer) and 11.7mW(without buffer) across dc to 3.5GHz with 100M-Hz sampling frequency. The implementation of a precise delay generator is also presented in the dissertation. It relies on an external reference clock to provide accurate timing against process, supply voltage and temperature variation through a negative feedback loop. The delay generator prototype has been verified having digital programmability and tunable delay step resolution. The relative delay shift from desired value is limited to within 0.2%.

Thesis (doctoral)--Universität Potsdam, 2002. / "April 2003"--P. [2] of cover. Lebenslauf. Includes bibliographical references (p. 93-101). Also available via the World Wide Web.

While dual-frequency GPS receivers have been used in space for more than two decades, the size, power, and cost of this technology is an important driver for future space missions. The growing availability of launch opportunities for very small satellites known as nanosatellites and CubeSats raises the possibility of more affordable access to space measurements if the observation quality is sufficient to support the user's needs. This thesis presents the initial development and testing of the Fast, Orbital, TEC, Observables, and Navigation (FOTON) receiver: a small, reconfigurable, dual-frequency, space-based GPS receiver. Originally developed as a science-grade software receiver for monitoring ionospheric scintillation and total electron content (TEC), this receiver was designed to provide high-quality GPS signal observations. The original receiver hardware was miniaturized and the software has been adapted for low earth orbit (LEO) operations. FOTON now fits within a 0.5U CubeSat form factor (8.3 x 9.6 x 3.8 cm), weighs 326 g, and consumes 4.5 W of instantaneous power, which can be reduced to <1 W orbit average power with on-off duty cycling. The receiver has been designed with commercial parts to keep manufacturing costs low. Significant testing of FOTON has been performed with live signals and with signals generated by a Spirent GPS signal simulator. Initial terrestrial tests demonstrate behavioral consistency with the original heritage high-performance receiver. Several LEO simulations are presented, demonstrating FOTON's single-frequency and dual-frequency-enhanced positioning down to 0.5 m and 1.5 m, respectively, which can be improved using Kalman filter based POD. FOTON's potential for GPS radio occultation observation is also demonstrated. In addition, its acquisition and reacquisition performance is presented; on average, FOTON's time to first fix is approximately 45 seconds. Finally, navigation in geostationary orbit (GEO), a challenging application for space-based GPS receivers, is demonstrated. Extensive testing demonstrates that FOTON is a robust, versatile, high-precision dual-frequency space receiver. Its low cost, size, weight, and power requirements are key enablers for future small-satellite missions. / text

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.