Regulator of G Protein Signaling 4 (RGS4) mediates motor defects in Parkinson's disease. Small molecule RGS4 inhibitors (e.g. CCG-50014) modify buried cysteine residues, but the structural and dynamic mechanisms underpinning specificity of inhibitors for RGS4 within the RGS family are poorly understood. We used NMR and other biophysical methods to examine ligand-induced structural changes and the dynamics of unliganded RGS4 and RGS8 that allow ligand binding. NMR and fluorescence spectroscopy data reveal details of the hidden, excited conformational state of RGS4 that exposes Cys148, one of the buried cysteines bound by inhibitors. We further show that specificity of RGS4 inhibitors is driven by differential accessibility of the target cysteine compared to its equivalent in RGS8. Cys148 is buried beneath the lid at the center the α4-α7 helix bundle, and this bundle is destabilized in RGS4 compared to RGS8. Notably, helix 6 is highly destabilized in RGS4 compared to RGS8 and is likely the key mediator of access to Cys148. Our findings provide key insight into the mechanism of allosteric RGS4 inhibition and show that dynamics drive inhibitory specificity among RGS proteins.

Duty cycle and frequency are important characteristics of periodic signals that are exploited to develop a variety of application circuits in IC design. Controlling the duty cycle and frequency provides a method to develop adaptable circuits for a variety of applications. These applications range from stable on-chip clock generation circuits, on-chip voltage regulation circuits, and Physical unclonable functions for hardware security applications. Ring oscillator circuits that are developed with CMOS inverter circuits provide a simple, versatile flexible method to generated periodic signals on an IC chip. A digitally controlled ring oscillator circuit can be adapted to control its duty cycle and frequency. This work describes a novel current starved ring oscillator, with digitally controlled current source based headers and footers, that is used to provide a versatile duty cycle and a precise frequency control. Using this novel circuit, the duty cycle and frequency can be adapted to a wide range of values. The proposed circuit achieves i) a controlled duty cycle that can vary between 20% and 90% with a high granularity and ii) a compensation circuit that guarantees a constant duty cycle under process, voltage, and temperature (PVT) variations. A novel application of the proposed PWM circuit is the design and demonstration of a reliable and reconfigurable Duty-cycle based Physical unclonable function (PUF). The proposed PWM based PUF circuit is demonstrated to work in a reliable and stable operation for a variety of process, voltage and temperature conditions with circuit implementations using 22nm and 32nm CMOS technologies. A comparative presentation of the duty cycle based PUF are provided using standard PUF figures of merits.

Distributed on-chip voltage regulation where multiple voltage regulators are distributed among different locations of the chip demonstrates advantages as compared to on-chip voltage regulation utilizing a single voltage regulator. Better on-chip voltage noise performance and faster transient response can be realized due to localized voltage regulation. Despite the advantages of distributed on-chip voltage regulation, unbalanced current sharing issue can occur among each voltage regulator, which has been demonstrated to deteriorate power conversion efficiency, stability, and reliability of the power delivery network. An effective balanced current sharing scheme that can be applied to most voltage regulator types is proposed to balance the current sharing. Furthermore, a relatively high on-chip temperature induced by increased power density leads to prominent voltage regulator performance degradations due to aging. The emerging type of digital low-dropout regulator is investigated regarding aging induced transient and steady state performance degradations. Reliability enhancement techniques for digital low-dropout regulators are developed and verified. Such techniques introduce negligible power and area overhead and do not affect the normal operations of digital low-dropout regulators. Reliability enhancement techniques also reduce the area overhead needed to mitigate aging induced performance degradations. Area overhead saving further translates into more space for increased number of distributed on-chip voltage regulators, enabling scalable on-chip voltage regulation.

A completely decomposable group is a direct sum of subgroups of the rationals. An almost completely decomposable group is a torsion free abelian group that contains a completely decomposable group as subgroup of finite index. Tight subgroups are maximal subgroups (with respect to set inclusion) among the completely decomposable subgroups of an almost completely decomposable group. In this dissertation we show an extended version of the theorem of Bezout, give a new criterion for the tightness of a completely decomposable subgroup, derive some conditions under which a tight subgroup is regulating and generalize a theorem of Campagna. We give an example of an almost completely decomposable group, all of whose regulating subgroups do not have a quotient with minimal exponent. We show that among the types of elements of a coset modulo a completely decomposable group there exists a unique maximal type and define this type to be -the- coset type. We give criteria for tightness and regulating in term of coset types as well as a representation of the type subgroups using coset types. We introduce the notion of reducible cosets and show their key role for transitions from one completely decomposable subgroup up to another one containing the first one as a proper subgroup. We give an example of a tight, but not regulating subgroup which contains the regulator. We develop the notion of a fully single covered subset of a lattice, show that V-free implies fully single covered, but not necessarily vice versa, and we define an equivalence relation on the set of all finite subsets of a given lattice. We develop some extension of ordinary Hasse diagrams, and apply the lattice theoretic results on the lattice of types and almost completely decomposable groups. / Eine vollständig zerlegbare Gruppe ist eine direkte Summe von Untergruppen der rationalen Zahlen. Eine fast vollständig zerlegbare Gruppe ist eine torsionsfreie abelsche Gruppe, die eine vollständig zerlegbare Gruppe als Untergruppe von endlichem Index enthält. Tight Untergruppen sind bezüglich Mengeninklusion maximale Elemente der Menge der vollständig zerlegbaren Untergruppen einer fast vollständig zerlegbaren Gruppe. In dieser Dissertation zeigen wir eine erweiterte Version des Satzes von Bezout, geben ein neues Kriterium an, mit dem festgestellt werden kann, ob eine Untergruppe tight ist, leiten daraus einige Bedingungen ab, unter denen eine tight Untergruppe regulierend ist, und verallgemeinern einen Satz von Campagna. Wir geben ein Beispiel einer fast vollständig zerlegbaren Gruppe an, deren sämtliche regulierende Untergruppen nicht minimalen Exponenten des Quotienten haben. Wir zeigen, daß unter den Typen der Elemente einer Nebenklasse modulo einer vollständig zerlegbaren Gruppe ein eindeutig definierter maximaler Typ existiert und nennen diesen Typen -den- Nebenklassentypen. Wir geben Kriterien für tight und regulierend mit Hilfe von Nebenklassentypen, sowie eine Darstellung der Typenuntergruppen. Wir führen den Begriff der reduziblen Nebenklassen ein und zeigen die Schlüsselrolle, die diese beim Übergang von einer vollständig zerlegbaren Untergruppe zu einer anderen, die die erste enthält, haben. Wir geben ein Beispiel einer tight Untergruppe an, die nicht regulierend ist, aber den Regulator enthält. Wir führen den Begriff einer "fully single covered" Untermenge eines Verbandes ein, zeigen daß V-frei "fully single covered" impliziert, aber nicht umgekehrt, und definieren eine Äquivalenzrelation auf der Menge aller endlichen Untermengen eines Verbandes. Wir entwickeln eine Erweiterung der üblichen Hasse Diagramme und wenden die verbandstheoretischen Ergebnisse auf die Typenmenge fast vollständig zerlegbarer Gruppen an.

Small satellites are becoming increasingly important to the aerospace industry mainly due to their significantly reduced development and launch cost as well as shorter development time frames. In order to meet the requirements imposed by critically limited resources of very small satellites, e.g. picosatellites, innovative approaches have to be taken in the design of effective subsystem technologies. This thesis presents the design of an active attitude determination and control system for flight testing on-board the picosatellite 'Compass-1' of the University of Applied Sciences Aachen, Germany. The spacecraft of the CubeSat class with a net spacecraft mass of only 1kg uses magnetic coils as the only means of actuation in order to satisfy operational requirements imposed by its imagery payload placed on a circular and polar Low Earth Orbit. The control system is capable of autonomously dissipating the tumbling rates of the spacecraft after launch interface separ ation and aligning the boresight of the payload into the desired nadir direction within a pointing error of approximately 10°. This nadir-pointing control is achieved by a full-state feedback Linear Quadratic Regulator which drives the attitude quaternion and their respective rates of change into the desired reference. The state of the spacecraft is determined by a static statistical QUEST attitude estimator processing readings of a three-axis magnetometer and a set of five sun sensors. Linear Floquet theory is applied to quantify the stability of the controller and a non-linear dynamics simulation is used to confirm that the attitude asymptotically converges to the reference in the absence of environmental disturbances. In the presence of disturbances the system under control suffers from fundamental underactuaction typical for purely magnetic attitude control but maintains satisfactory alignment accuracies within operational boundaries.

<p>Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry. </p><p>In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared. </p><p>A functionality to detect when the lifetime of the battery is about to run out was also developed.</p>

<p>This master thesis covers the development of an automatic tuning process for the existing speed controller for drive systems. The drive systems are resonant two-mass systems where a motor is used to drive a load connected by a shaft. The developed method relies heavily on system identification and the construction of a complete mechanical model of the process. With this approach, the common problem with poor load speed control that derives from measuring only the motor speed can be addressed and solved for a majority of such processes.</p><p>The automatic tuning method has along with general test functions been implemented in a complete tool for automatic tuning, testing and performance evaluation and reporting for drive systems.</p>

The sale of hybrid electric vehicles (HEVs) has increased tenfold from the year 2001 to 2009 [1]. With this the demand for high temperature electronics has also increased dramatically making, high temperature electronics for HEV applications desirable in the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. Power converters (i.e. DC-DC converter, DC-AC inverter) inside the HEVs require gate drivers to control the power switches. An integrated gate driver circuit has been realized in 0.8-um BCD-on-SOI process. This gate driver IC needs a step-down voltage regulator to convert the unregulated high input DC voltage (VDDH) to a regulated nominal CMOS voltage (i.e. 5 V). This step-down voltage regulator will supply voltage to the low-side buffer (pre-driver) and other digital and analog circuits inside the gate driver ICs. A linear voltage regulator is employed to accomplish this task; however, very few publications on high temperature voltage regulators are available. This research presents a high temperature linear voltage regulator designed and fabricated in a commercially available 0.8-um BCD-on-SOI process. SOI processes typically offer reduced junction leakage current by three orders of magnitude compared to the bulk-CMOS processes at temperatures beyond 150°C. In addition, a pole swap compensation technique is utilized to achieve stability over a wide range (four decades) of load current. The error amplifier inside the regulator is designed using an inversion coefficient based design methodology, and a temperature stable current reference is used to bias the error amplifier. The linear regulator provides an output voltage of 5.3 V at room temperature and can supply a maximum load current of 200 mA.

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

At the department of Electronic Warfare Assessments at the Swedish Defence Research Agency in Linköping one of the activities is modelling and simulation of the duel between a robot and a target. The aim with this Master's thesis is to develop a simulation model of an hovering helicopter. First a theoretical description of the forces and moments acting on an helicopter is given. Then the equations of motion are derived. These equations are simplified to be valid only for a hovering helicopter and the result is a mathematical model. The mathematical model is the basis for the design of a regulator, whos task is to bring the helicpoter to equilibrium and keep it hovering. Two different regulators are implemented and tested for several cases when different disturbances are acting on the helicopter. The matemathical model and one of the regulators are implemented in a simulation program and the results of the simulations are visualized in a graphical interface.