Zugl.: Dortmund, Techn. Univ., Diss., 2008

Zugl.: Bochum, Univ., Diss., 2009

Die Entwicklung von Telekommunikationsnetzwerken unterliegt einer Reihe von Herausforderungen. Hohe Komplexität, hohe Bandbreite mit veränderlichen Anforderungen, kurze Entwicklungszyklen und sich ständig ändernde Marktanforderungen sind verbunden mit sich immer schneller ändernden Standards. Daraus resultieren hohe Risiken für die Entwicklung von Kommunikationslösungen. Die Kombination von rekonfigurierbaren und ASIC-Technologien bietet eine Möglichkeit, die Vorteile der ASICTechnologie weitestgehend zu erhalten und dem Risiko von Standardänderungen und Designfehlern zu begegnen. Dieser Beitrag stellt anhand eines Ethernet-verarbeitenden SoC eine Möglichkeit vor, paketorientierte Netzwerkknoten hinsichtlich zukünftiger Änderungen flexibel zu implementieren. Der Netzwerkknoten kann über spezielle Ethernet-Pakete rekonfiguriert und somit an geänderte Anforderungen angepasst werden.

The modern embedded system is getting more complicated due to the functional requirements of the system are rapidly increasing. The modern system must have more reliable, as it deals with a lot of data. The distributed systems are used in variety technologies field due to it has more reliable than single control unit. It can transfer task to other processing unit when the one part of system failed while the single control unit failed cause the system to stop operate. The FPGA are being used increasingly in the distributed system due to the benefit of FPGA over microcontroller and ASIC. FPGA is flexible than ASIC due to the ability to reconfiguration its function. FPGA processes the data in parallel, therefore, it computes the data faster than the microcontroller that computes the data in concurrence. The flexibility of FPGA supports the development of reliable distributed system. When one of FPGA failed, the other FPGA can reconfiguration itself to operate on the task of the failed FPGA. The method to reconfigure the FPGA structure is a process of loading new bitstream file into FPGA. For generating variety configurations of distributed system. The developer must develop number of bitstream file according to number of reconfiguration designs. Although the FPGA is flexible and can reconfiguration anytime, the development process of configuration file is a redundancy workload. One FPGA design structure equals one configuration file. This project focus on reduce the redundancy workload, therefore, it can reduce the development time and make the development project launching faster. This virtual partial reconfiguration framework is developed to assist the developer in generating many configuration files without coding. The framework will determine all possible combination of modules and generates all combination design files. One set of the design contain the VHDL file and UCF file. The developer can use these files to synthesise in FPGA vendor development tool and generate bitstream. This virtual partial reconfiguration framework also provides the partial reconfiguration benefits except runtime reconfiguration.

Prozesse, seien es Geschäfts- oder Produktionsprozesse, sind ständigen Änderungen unterworfen. Für Unternehmen gilt es, sich im Rahmen von Geschäftsprozessen immer wieder neuen Marktgegebenheiten, Gesetzen oder Kunden anzupassen. Auch Produktionsprozesse müssen bspw. für die Verarbeitung neuer Materialien zugeschnitten werden. Die vorliegende Arbeit beschreibt deshalb, einen umfassenden Ansatz für den Umgang mit Änderungen bzw. Rekonfigurationen von Workflows zu entwickeln. Dieser zeichnet sich durch zwei Schwerpunkte aus: (1) Vollständige Rekonfiguration aller Workflowperspektiven und (2) eine reflexive autonome Steuerung der Rekonfigurationen.

Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.

Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.

FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing. / FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.

Die fortschreitenden Entwicklungen in der Mikro- und Nanotechnologie erfordern eine solide Unterstützung durch Simulationen. Numerische Bauelementesimulationen waren und sind dabei unerlässliche Werkzeuge, die jedoch zunehmend an ihre Grenzen kommen. So basieren sie auf Parametern, die für beliebige Atomanordnungen nicht verfügbar sind, und scheitern für stark verkleinerte Strukturen infolge zunehmender Relevanz von Quanteneffekten. Diese Arbeit behandelt den Transport in Siliziumnanodrähten sowie durch NiSi2-Si-Grenzflächen. Dichtefunktionaltheorie wird dabei verwendet, um die stabile Atomanordnung und alle für den elektronischen Transport relevanten quantenmechanischen Effekte zu beschreiben. Bei der Untersuchung der Nanodrähte liegt das Hauptaugenmerk auf der radialen Abhängigkeit der elektronischen Struktur sowie deren Änderung bei Variation des Durchmessers. Dabei zeigt sich, dass der Kern der Nanodrähte für den Ladungstransport bestimmend ist. Weiterhin kann ein Durchmesser von ungefähr 5 nm identifiziert werden, oberhalb dessen die Zustandsdichte im Nanodraht große Ähnlichkeiten mit jener des Silizium-Volumenkristalls aufweist und der Draht somit zunehmend mit Näherungen für den perfekt periodischen Kristall beschrieben werden kann. Der Fokus bei der Untersuchung der NiSi2-Si-Grenzflächen liegt auf der Symmetrie von Elektron- und Lochströmen im Tunnelregime, welche für die Entwicklung von rekonfigurierbaren Feldeffekttransistoren besondere Relevanz hat. Verschiedene NiSi2-Si-Grenzflächen und Verzerrungszustände werden dabei systematisch untersucht. Je nach Grenzfläche ist die Symmetrie dabei sehr unterschiedlich und zeigt auch ein sehr unterschiedliches Verhalten bei externer Verzerrung. Weiterhin werden grundlegende physikalische Größen mit Bezug zu NiSi2-Si-Grenzflächen betrachtet. So wird beispielsweise die Stabilität anhand von Grenzflächen-Energien ermittelt. Am stabilsten sind {111}-Grenzflächen, was deren bevorzugtes Auftreten in Experimenten erklärt. Weitere wichtige Größen, deren Verzerrungsabhängigkeit untersucht wird, sind die Schottky-Barrierenhöhe, die effektive Masse der Ladungsträger sowie die Austrittsarbeiten von NiSi2- und Si-Oberflächen. Ein Beitrag zur Modellentwicklung numerischer Bauelementesimulationen wird durch einen Vergleich zwischen den Ergebnissen von Dichtefunktionaltheorie-basierten Transportrechnungen und denen eines vereinfachten Models basierend auf der Wentzel-Kramers-Brillouin-Näherung geliefert. Diese Näherung ist Teil vieler numerischer Bauelementesimulatoren und erlaubt die Berechnung des Tunnelstroms basierend auf grundlegenden physikalischen Größen. Der Vergleich ermöglicht eine Evaluierung des vereinfachten Models, welches anschließend genutzt wird, um den Einfluss der grundlegenden physikalischen Größen auf den Tunneltransport zu untersuchen.:Index of Abbreviations 1. Introduction 2. Silicon Based Devices and Silicon Nanowires 2.1. Introduction 2.2. The Reconfigurable Field-effect Transistor 2.2.1. Design and Functionality 2.2.2. Fabrication 2.3. Overview Over Silicon Nanowires 2.3.1. Geometric Structure 2.3.2. Fabrication Techniques 2.3.3. Electronic Properties 3. Simulation Tools 3.1. Introduction 3.2. Electronic Structure Calculations 3.2.1. Introduction and Basis Functions 3.2.2. Density Functional Theory 3.2.3. Description of Exchange and Correlation Effects 3.2.4. Practical Aspects of Density Functional Theory 3.3. Electron Transport 3.3.1. Introduction 3.3.2. Scattering Theory 3.3.3. Wentzel-Kramers-Brillouin Approximation for a Triangular Barrier 3.3.4. Non-equilibrium Green’s Function Formalism A. Radially Resolved Electronic Structure and Charge Carrier Transport in Silicon Nanowires A.1. Introduction A.2. Model System A.3. Results and Discussion A.4. Summary and Conclusions A.5. Appendix A: Computational Details A.6. Appendix B: Supplementary Material A.6.1. Comparison of the Band Gap Between Relaxed and Unrelaxed SiNWs A.6.2. Band Structures for Some of the Calculated SiNWs A.6.3. Radially Resolved Density of States for Some of the Calculated SiNWs B. Electron Transport Through NiSi2-Si Contacts and Their Role in Reconfigurable Field-effect Transistors B.1. Introduction B.2. Model for Reconfigurable Field-effect Transistors B.2.1. Atomistic Quantum Transport Model to Describe Transport Across the Contact Interface B.2.2. Simplified Compact Model to Calculate the Device Characteristics B.3. Results and Discussion B.3.1. Characteristics of a Reconfigurable Field-effect Transistor B.3.2. Variation of the Crystal Orientations and Influence of the Schottky Barrier B.3.3. Comparison to Fabricated Reconfigurable Field-effect Transistors B.4. Summary and Conclusions B.5. Appendix: Supplementary Material B.5.1. Band Structure and Density of States of the Contact Metal B.5.2. Relaxation Procedure B.5.3. Total Transmission Through Multiple Barriers C. Formation and Crystallographic Orientation of NiSi2-Si Interfaces C.1. Introduction C.2. Fabrication and characterization methods C.3. Model System and Simulation Details C.4. Results and discussion C.4.1. Atomic structure of the interface C.4.2. Discussion of ways to modify the interface orientation C.5. Summary C.6. Appendix: Supplementary Material D. NiSi2-Si Interfaces Under Strain: From Bulk and Interface Properties to Tunneling Transport D.1. Introduction D.2. Model System and Simulation Approach D.3. Computational Details D.3.1. Electronic Structure Calculations (Geometry Relaxations) D.3.2. Electronic Structure Calculations (Electronic Structure) D.3.3. Device Calculations D.4. Tunneling Transport From First-principles Calculations D.4.1. Evaluation of the Current D.4.2. Isotropic Strain D.4.3. Anisotropic Strain D.5. Transport Related Properties and Effective Modeling Schemes D.5.1. Schottky Barrier Height D.5.2. Simplified Transport Model D.5.3. Models for the Schottky Barrier Height D.6. Summary and Conclusions D.7. Appendix: Supplementary Material D.7.1. Schottky Barriers of the {110} Interface Under Anisotropic Strain D.7.2. Silicon Band Structure, Electric Field, and Number of Transmission Channels D.7.3. k∥-resolved Material Properties D.7.4. Evaluation of the Work Functions and Electron Affinities D.7.5. Verification of the Work Function Calculation 4. Discussion 5. Ongoing Work and Possible Extensions 6. Summary Bibliography List of Figures List of Tables Acknowledgements Selbstständigkeitserklärung Curriculum Vitae Scientific Contributions / The ongoing developments in micro- and nanotechnologies require a profound support from simulations. Numerical device simulations were and still are essential tools to support the device development. However, they gradually reach their limits as they rely on parameters, which are not always available, and neglect quantum effects for small structures. This work addresses the transport in silicon nanowires and through NiSi2-Si interfaces. By using density functional theory, the atomic structure is considered, and all electron transport related quantum effects are taken into account. Silicon nanowires are investigated with special attention to their radially resolved electronic structure and the corresponding modifications when the silicon diameter is reduced. The charge transport occurs mostly in the nanowire core. A diameter of around 5 nm can be identified, above which the nanowire core exhibits a similar density of states as bulk silicon. Thus, bulk approximations become increasingly valid above this diameter. NiSi2-Si interfaces are studied with focus on the symmetry between electron and hole currents in the tunneling regime. The symmetry is especially relevant for the development of reconfigurable field-effect transistors. Different NiSi2-Si interfaces and strain states are studied systematically. The symmetry is found to be different between the interfaces. Changes of the symmetry upon external strain are also very interface dependent. Furthermore, fundamental physical properties related to NiSi2-Si interfaces are evaluated. The stability of the different interfaces is compared in terms of interface energies. {111} interfaces are most stable, which explains their preferred occurrence in experiments. Other properties, whose strain dependence is studied, include the Schottky barrier height, the effective mass of the carriers, and work functions. A contribution to the development of numerical device simulators will be given by comparing the results from density functional theory based transport calculations and a model based on the Wentzel-Kramers-Brillouin approximation. This approximation, which is often employed in numerical device simulators, offers a relation between interface properties and the tunneling transport. The comparison allows an evaluation of the simplified model, which is then used to investigate the relation between the fundamental physical properties and the tunneling transport.:Index of Abbreviations 1. Introduction 2. Silicon Based Devices and Silicon Nanowires 2.1. Introduction 2.2. The Reconfigurable Field-effect Transistor 2.2.1. Design and Functionality 2.2.2. Fabrication 2.3. Overview Over Silicon Nanowires 2.3.1. Geometric Structure 2.3.2. Fabrication Techniques 2.3.3. Electronic Properties 3. Simulation Tools 3.1. Introduction 3.2. Electronic Structure Calculations 3.2.1. Introduction and Basis Functions 3.2.2. Density Functional Theory 3.2.3. Description of Exchange and Correlation Effects 3.2.4. Practical Aspects of Density Functional Theory 3.3. Electron Transport 3.3.1. Introduction 3.3.2. Scattering Theory 3.3.3. Wentzel-Kramers-Brillouin Approximation for a Triangular Barrier 3.3.4. Non-equilibrium Green’s Function Formalism A. Radially Resolved Electronic Structure and Charge Carrier Transport in Silicon Nanowires A.1. Introduction A.2. Model System A.3. Results and Discussion A.4. Summary and Conclusions A.5. Appendix A: Computational Details A.6. Appendix B: Supplementary Material A.6.1. Comparison of the Band Gap Between Relaxed and Unrelaxed SiNWs A.6.2. Band Structures for Some of the Calculated SiNWs A.6.3. Radially Resolved Density of States for Some of the Calculated SiNWs B. Electron Transport Through NiSi2-Si Contacts and Their Role in Reconfigurable Field-effect Transistors B.1. Introduction B.2. Model for Reconfigurable Field-effect Transistors B.2.1. Atomistic Quantum Transport Model to Describe Transport Across the Contact Interface B.2.2. Simplified Compact Model to Calculate the Device Characteristics B.3. Results and Discussion B.3.1. Characteristics of a Reconfigurable Field-effect Transistor B.3.2. Variation of the Crystal Orientations and Influence of the Schottky Barrier B.3.3. Comparison to Fabricated Reconfigurable Field-effect Transistors B.4. Summary and Conclusions B.5. Appendix: Supplementary Material B.5.1. Band Structure and Density of States of the Contact Metal B.5.2. Relaxation Procedure B.5.3. Total Transmission Through Multiple Barriers C. Formation and Crystallographic Orientation of NiSi2-Si Interfaces C.1. Introduction C.2. Fabrication and characterization methods C.3. Model System and Simulation Details C.4. Results and discussion C.4.1. Atomic structure of the interface C.4.2. Discussion of ways to modify the interface orientation C.5. Summary C.6. Appendix: Supplementary Material D. NiSi2-Si Interfaces Under Strain: From Bulk and Interface Properties to Tunneling Transport D.1. Introduction D.2. Model System and Simulation Approach D.3. Computational Details D.3.1. Electronic Structure Calculations (Geometry Relaxations) D.3.2. Electronic Structure Calculations (Electronic Structure) D.3.3. Device Calculations D.4. Tunneling Transport From First-principles Calculations D.4.1. Evaluation of the Current D.4.2. Isotropic Strain D.4.3. Anisotropic Strain D.5. Transport Related Properties and Effective Modeling Schemes D.5.1. Schottky Barrier Height D.5.2. Simplified Transport Model D.5.3. Models for the Schottky Barrier Height D.6. Summary and Conclusions D.7. Appendix: Supplementary Material D.7.1. Schottky Barriers of the {110} Interface Under Anisotropic Strain D.7.2. Silicon Band Structure, Electric Field, and Number of Transmission Channels D.7.3. k∥-resolved Material Properties D.7.4. Evaluation of the Work Functions and Electron Affinities D.7.5. Verification of the Work Function Calculation 4. Discussion 5. Ongoing Work and Possible Extensions 6. Summary Bibliography List of Figures List of Tables Acknowledgements Selbstständigkeitserklärung Curriculum Vitae Scientific Contributions

Ausgehend von einer modularen Plattform zur Erfassung und Verarbeitung von Sensordaten bereichert die vorliegende Dissertationsschrift den Systementwurf eingebetteter Systeme um neue Facetten. Ihr besonderer Fokus liegt dabei auf rekonfigurierbaren Architekturen und Linux-basierten Systemen. Ein wesentlicher Beitrag ist die Darstellung und Diskussion von Konzepten und Architekturen vorgenannter Systeme durch ihre Betrachtung auf einer hohen Abstraktionsebene. Dazu schafft die Arbeit ein umfassendes Verständnis für Kommunikation und Konfiguration in heterogenen rekonfigurierbaren Systemen und überträgt die Erkenntnisse auf das Linux-Betriebssystem. Es erfolgt außerdem eine systematische Darstellung der etablierten Zusammenhänge und Abläufe beim Software-, Paket- und Versionsmanagement im Linux-Umfeld. Zur Verbesserung des Entwurfsflusses werden Konzepte und ein geeignetes Werkzeug zur High-Level Spezifikation von Linux-Systemen dargestellt. Die in der Arbeit gewonnenen wissenschaftlichen Erkenntnisse werden hinsichtlich praktischer Relevanz evaluiert und durch prototypische Implementierungen verifiziert. / Based on a modular platform for recording and processing of sensor data the present thesis enriches the field of system design of embedded systems with new facets. Its particular focus is on reconfigurable architectures and Linux-based systems. A major contribution is the presentation and discussion of concepts and architectures of aforementioned systems by investigating them on a high level of abstraction. To achieve this, the work creates a comprehensive understanding of communication and configuration in heterogeneous reconfigurable systems. This knowledge is transferred on the Linux operating system. In addition, a systematic presentation of the established relationships and processes in software, package and version management in the Linux environment takes place. To improve the design flow of Linux systems, the thesis presents appropriate concepts as well as a tool for high-level specification of embedded Linux systems. The gained scientific findings are evaluated in terms of practical relevance and verified by prototype implementations.