The development of state-of-the-art AlGaN/GaN high electron mobility transistors (HEMTs) has shown much promise for advancing future RF and microwave communication systems. These revolutionary devices demonstrate great potential and superior performance and many commercial companies have demonstrated excellent reliability results based on multiple temperature accelerated stress testing. However, a physical understanding of the various reliability limiting mechanisms is lacking and the role and relative contribution of the various intrinsic material factors, such as physical stress and strain has not been clearly explained in the literature. Part of issues that impact device reliability are the mechanical stresses induced in the devices as well as the self-heating that also limit device performance. Thus, quantification of stress and temperature in AlGaN/GaN HEMTs is of great importance. To address some of the needs for metrology to quantify stress in AlGaN/GaN HEMTs, micro-Raman spectroscopy and micro-photoluminescence (micro-PL) were utilized to quantify the residual stress in these devices. Through the use of micro-Raman and micro-PL optical characterization methods, mapping of the vertical and lateral stress distributions in the device channels was performed. Results show that stress can be influenced by the substrate material as well as patterned structures including metal electrodes and passivation layers. Previously developed and reported micro-Raman thermometry methods require an extensive calibration process for each device investigated. To improve the implementation of micro-Raman thermometry, a method was developed which offers both experimental simplicity and high accuracy in temperature results utilizing a universal calibration method that can be applied to a broad range of GaN based devices. This eliminates the need for performing calibration on different devices. By utilizing this technique, it was revealed that under identical power dissipation levels, the bias conditions (combination of Vgs and Vds) alter the heat generation profile across the conductive channel and thus influence the degree of device peak temperature. The role of stress in the degradation of AlGaN/GaN HEMTs was also explored. A combined analysis using micro-Raman spectroscopy, coupled electro-thermo-mechanical simulation, and electrical step stress tests was conducted to investigate the link between performance degradation and the evolution of total stress in devices. It was found that in addition to stresses arising from the inverse piezoelectric effect, the substrate induced residual stress and the operational themo-elastic stress in the AlGaN layer play a major role in determining the onset of mechanically driven device degradation. Overall, these experiments were the first to suggest that a critical level of stress may exist at which point device degradation will start to occur. The optical characterization methods developed in this study show the ability to reveal unprecedented relationships between temperature/stress and device performance/reliability. They can be used as effective tools for facilitating improvement of the reliability of future AlGaN/GaN HEMTs.

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.

The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. This thesis investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs, as the topic has yet to be explored systematically. An emphasis was placed on bias-stress measurements over time in order to obtain information on the physical mechanisms of instability. Drain current was measured over various intervals of time to track the degradation of devices due to metastability, and results were then compared across devices of various sizes under tensile, compressive, and zero strain. Transfer characteristics of the TFTs were also measured under the different conditions, to allow for extraction of parameters that would provide insight into the instability mechanisms. In addition to parameter extraction, the degradation and recovery of TFT output current was quantitatively compared for various bias-stress times across the different levels of strain. Finally, the instability mechanisms are modelled with a Markov system to further examine the effect of strain on long-term TFT operation. From the analysis of results, it was found that shallow charge trapping in the dielectric is the main mechanism of instability for short bias stress times, and did not seem to be greatly affected by strain. For longer bias stress times of over 10000 seconds, defect creation in the a-Si:H becomes a more significant contributor to instability. Both tension and compression increased defect creation compared to TFTs with zero applied strain. Compression appeared to cause the greatest increase in the rate of defect formation, likely by weakening Si-Si bonds in the a-Si:H. Tension appeared to cause a less significant increase, possibly due to a strengthening of some proportion of the Si-Si bonds caused by the slight elongation of bond length or because the applied tension relieves intrinsic compressive stress in a-Si:H film. A longer conduction path and greater dielectric area appears to increase the bias-stress and strain-related effects. Therefore reducing device size should increase the reliability of flexible TFTs.

The thesis deals with study of high-temperature alloying process of power semiconductor devices. Mechanical durability and loss heat extraction is achieved via contacting silicon devices on molybdenum electrode in vacuum alloying furnace. Properties of alloy contact determine electrical, geometrical and mechanical parameters of device and are related with durability of device under heavy load during operation in various industrial machines or transport vehicles. Process parameters are evaluated in terms of input materials and their preparation along with temperature ramp profile and conditions in vacuum furnace. Test samples are analyzed to assess their electrical and geometrical parameters and selected samples underwent element analysis of alloy contact. Optimal process parameters are estimated according to analysis of experiments.

No description available.

We report on the observation of lasing in cuprous iodide (CuI) microwires. A vapor-phase transport growth procedure was used to synthesize CuI microwires with low defect concentration. The crystal structure of single microwires was determined to be of zincblende-type. The high optical quality of single microwires is indicated by the observed series of excitonic emission lines as well as by the formation of gain under optical excitation. Lasing of triangular whispering-gallery modes in single microwires is demonstrated for fs- and ns-excitation from cryogenic temperatures up to 200 K. Timeresolved micro-photoluminescence studies reveal the dynamics of the laser process on the time scale of several picoseconds.

No description available.

No description available.

This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of low-temperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ~80% bulk density at temperatures no more than 300°C. It has been found that the low-temperature sintered silver has better electrical, thermal and overall thermomechanical properties compared with the existing semiconductor device interconnecting materials such as solder alloys and conductive epoxies. After solving the organic burnout problems associated with the covered sintering, a lead-free semiconductor device interconnect technology has been designed to be compatible with the existing surface-mounting techniques with potentially low-cost. It has been found that the low-temperature sintered silver joints have high electrical, thermal, and mechanical performance. The reliability of the silver joints has also been studied by the 50-250°C thermal cycling experiment. Finally, the bonging strength drop of the silver joints has been suggested to be ductile fracture in the silver joints as micro-voids nucleated at microscale grain boundaries during the temperature cycling. The low-temperature silver sintering technology has enabled some benchmark packaging concepts and substantial advantages in future applications. / Ph. D.

The work deals with the capacitance measurement of high-voltage PN junctions. The work is divided into theoretical and practical parts. The theoretical part presents insight into the fundamental properties of PN junctions and methods for measuring of the capacitance of PN junctions, primarily by C-V measurement. In the practical part, several kinds of measuring circuits are introduced and a suitable method of measurement is found. The calculations of basic parameters - the width of the base and resistivity are presented and discussed. The results were compared with the values obtained by calculation from the technological parameters of the junction.