abstract: Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases. / Dissertation/Thesis / M.S. Materials Science and Engineering 2013

Advances in power electronic systems, especially those in hybrid and electric automobiles and renewable power generation systems, demand high blocking voltage, fast switching performance and low thermal budget from power semiconductor devices. State-of-the--art, silicon based power semiconductor devices are limited by material properties in meeting these demands. Due to the relatively low critical electric field, the on-resistance of the devices is high, and increases significantly with blocking voltage. As a result, current silicon (Si) power MOSFETs rated at above 600 V suffer from unacceptably high conduction losses. Innovative designs, such as the insulated gate bipolar transistor (IGBT), have been developed which use conductivity modulation through the injection of minority carriers to reduce on-resistance. But the involvement of minority carriers gives rise to stored charge and a turn-off delay, dramatically increasing switching losses compared to unipolar devices. Silicon carbide (SiC), a wide band gap semiconductor provides an alternative to Si, and offers a 7x higher electric field strength, 2x higher saturation velocity, and 3x higher thermal conductivity. A thinner, more heavily doped drift region is required for a SiC power device for a particular voltage, which reduces on-resistance and power consumption. However, the channel resistance of SiC metal oxide semiconductor field effect transistors (MOSFETs) is high due to the poor quality of the dielectric-semiconductor interface. Thus the SiC MOSFET fails to live up to the full promise of the material. Minimization of the channel resistance is essential, especially for applications requiring blocking voltages under 1 kV, where this component dominates others. In this work, a novel tri-gate SiC MOSFET is proposed to address this issue. This new structure utilizes both the conventional horizontal surface as well as the sidewalls of a trench to increase the effective width of the channel without increasing the device area. With proper optimization, it should be possible to achieve 3x lower specific on-resistance compared to current SiC unipolar power devices.

No description available.

abstract: Silicon photonic technology continues to dominate the solar industry driven by steady improvement in device and module efficiencies. Currently, the world record conversion efficiency (~26.6%) for single junction silicon solar cell technologies is held by silicon heterojunction (SHJ) solar cells based on hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si). These solar cells utilize the concept of carrier selective contacts to improve device efficiencies. A carrier selective contact is designed to optimize the collection of majority carriers while blocking the collection of minority carriers. In the case of SHJ cells, a thin intrinsic a-Si:H layer provides crucial passivation between doped a-Si:H and the c-Si absorber that is required to create a high efficiency cell. There has been much debate regarding the role of the intrinsic a-Si:H passivation layer on the transport of photogenerated carriers, and its role in optimizing device performance. In this work, a multiscale model is presented which utilizes different simulation methodologies to study interfacial transport across the intrinsic a-Si:H/c-Si heterointerface and through the a-Si:H passivation layer. In particular, an ensemble Monte Carlo simulator was developed to study high field behavior of photogenerated carriers at the intrinsic a-Si:H/c-Si heterointerface, a kinetic Monte Carlo program was used to study transport of photogenerated carriers across the intrinsic a-Si:H passivation layer, and a drift-diffusion model was developed to model the behavior in the quasi-neutral regions of the solar cell. This work reports de-coupled and self-consistent simulations to fully understand the role and effect of transport across the a-Si:H passivation layer in silicon heterojunction solar cells, and relates this to overall solar cell device performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

Bidirectional power switching devices are needed in many power management applications, particularly in lithium-ion battery protection circuitry. A monolithic bidirectional power switch fabricated with a simplified CMOS technology is introduced in this dissertation. Throughout the design process, ISE TCAD tool plays an important role. Design variables are carefully analyzed to improve the device performance or yield the best trade off. Optimization is done with the help of TCAD simulation and theoretical calculations. The device has been successfully fabricated using simplified 0.5 micron CMOS process. The experimental result shows a breakdown voltage of 25V. Due to the interdigitated source to source design, the inter-terminal current flowing path is effectively reduced to a few microns. The experimental result shows an ultra low specific on resistance. In comparison with other bi-directional power semiconductor switches by some major semiconductor manufacturers, the proposed BDS device has less than one half of the specific on resistance, thus substantially lower on state power loss of the switch. The proposed BDS device has a unique NPNPN structure, in comparison with NPNP structure, which is the analytical structure for CMOS latch-up, the proposed device inherently exhibits a better latch up immunity than CMOS inverter, thanks to the negative feed back mechanism of the extra NPN parasitic BJT transistor. In order to implement the device into simulators like PSPICE or Cadence IC Design, a compact model named variable resistance model has been built. This simple analytical model fits quite well with experimental data, and can be easily implemented by Verilog-A or other hardware description languages. Also, macro modeling is possible provided that the model parameters can be extracted from experimental curves. Several advanced types of BDS devices have been proposed, they exceed the basic BDS design in terms of breakdown voltage and /or on resistance. These advanced structures may be prominent for further improvement of the basic BDS device to a higher extend. Some cell phone providers such as Nokia is already asking for higher breakdown voltage of BDS device, due to the possibility of incidentally insert the battery pack into the cell phone with wrong pin polarity. Hopefully, the basic BDS design or one of these advanced types may eventually be implemented into the leading brand cell phone battery packs.

The objectives of this investigation are to develop a precise, non-destructive single crystal stress measurement technique, develop a model to explain the phenomenon known as 3power slump2, and investigate the role of device processing on wafer breakage. All three objectives were successfully met. The single crystal stress technique uses a least squares analysis of X-ray diffraction data to calculate the full stress tensor. In this way, precise non-destructive stress measurements can be made with known error bars. Rocking curve analysis, stress gradient corrections, and a data reliability technique were implemented to ensure that the stress data are correct. A theory was developed to explain 3power slump2, which is a rapid decrease in the amplifying properties of microwave amplifier circuits during operation. The model explains that for the particular geometry and bias configuration of the devices studied in this research, power slump is linearly related to shear stress at values of less than 90 MPa. The microscopic explanation of power slump is that radiation enhanced dislocation glide increases the kink concentration, thereby increasing the generation center concentration in the active region of the device. These generation centers increase the total gate current, leading to a decrease in the amplifying properties of the device. Passivation layer processing has been shown to both reduce the fracture strength and increase the residual stress in GaAs wafers, making them more susceptible to wafer breakage. Bare wafers are found to have higher fracture strength than passivated wafers. Bare wafers are also found to contain less residual stress than SiON passivated wafers, which, in turn, are found to have less stress than SiN passivated wafers. Topographic imaging suggests that SiN passivated wafers have larger flaws than SiON passivated wafers, and that the distribution of flaw size among SiN passivated wafers is wider than the distribution of flaws in SiON passivated wafers. These flaws are believed to lead to breakage of the device during processing, resulting in low fabrication yield. Both the power slump model and the wafer breakage data show that these phenomena are dependent on residual stress developed in the substrate during device fabrication. Reduction of process-induced residual stress should therefore simultaneously decrease wafer breakage rates and reduce power slump during device fabrication and operation. / Ph. D.

The next generation of power converters not only must meet the characteristics demanded by the load, but also has to meet some specific requirements like limited space and high ambient temperature etc. This needs the power converter to achieve high power density and high temperature operation. It is usually required that the active power devices operate at higher switching frequencies to shrink the passive components volume. The power semiconductor devices for high frequency high density power converter applications have been investigated. Firstly, the methodology is developed to evaluate the power semiconductor devices for high power density applications. The power density figure of merit (PDFOM) for power MOSFET and IGBT are derived from the junction temperature rise, power loss and package points of view. The device matrices are generated for device comparison and selection to show how to use the PDFOM. A calculation example is given to validate the PDFOM. Several semiconductor material figures of merit are also proposed. The wide bandgap materials based power devices benefits for power density are explored compared to the silicon material power devices. Secondly, the high temperature operation characteristics of power semiconductor devices have been presented that benefit the power density. The electrical characteristics and thermal stabilities are tested and analyzed, which include the avalanche breakdown voltage, leakage current variation with junction temperature rise. To study the thermal stability of power device, the closed loop thermal system and stability criteria are developed and analyzed. From the developed thermal stability criterion, the maximum switching frequency can be derived for the converter system design. The developed thermal system analysis approach can be extended to other Si devices or wide bandgap devices. To fully and safely utilize the power devices the junction temperature prediction approach is developed and implemented in the system test, which considers the parasitic components inside the power MOSFET module when the power MOSFET module switches at hundreds of kHz. Also the thermal stability for pulse power application characteristics is studied further to predict how the high junction temperature operation affects the power density improvement. Thirdly, to develop high frequency high power devices for high power high density converter design, the basic approaches are paralleling low current rating power MOSFETs or series low voltage rating IGBTs to achieve high frequency high power output, because power MOSFETs and low voltage IGBTs can operate at high switching frequency and have better thermal handling capability. However the current sharing issues caused by transconductance, threshold voltage and miller capacitance mismatch during conduction and switching transient states may generate higher power losses, which need to be analyzed further. A current sharing control approach from the gate side is developed. The experimental results indicate that the power MOSFETs can be paralleled with proper gate driver design and accordingly the switching losses are reduced to some extent, which is very useful for the switching loss dominated high power density converter design. The gate driving design is also important for the power MOSFET module with parallel dice inside thus increased input capacitance. This results in the higher gate driver power loss when the traditional resistive gate driver is implemented. Therefore the advanced self-power resonant gate driver is investigated and implemented. The low gate driver loss results in the development of the self-power unit that takes the power from the power bus. The overall volume of the gate driver can be minimized thus the power density is improved. Next, power semiconductor device series-connection operation is often used in the high power density converter to meet the high voltage output such as high power density boost converter. The static and dynamic voltage balancing between series-connected IGBTs is achieved using a hybrid approach of an active clamp circuit and an active gate control. A Scalable Power Semiconductor Switch (SPSS) based on series-IGBTs is developed with built-in power supply and a single optical control terminal. An integrated package with a common baseplate is used to achieve a better thermal characteristic. These design features allow the SPSS unit to function as a single optically controlled three-terminal switching device for users. Experimental evaluation of the prototype SPSS shows it fully achieved the design objectives. The SPSS is a useful power switch concept for building high power density, high switching frequency and high voltage functions that are beyond the capability of individual power devices. As conclusions, in this dissertation, the above-mentioned issues and approaches to develop high density power converter from power semiconductor devices standpoint are explored, particularly with regards to high frequency high temperature operation. To realize such power switches the related current sharing, voltage balance and gate driving techniques are developed. The power density potential improvements are investigated based on the real high density power converter design. The power semiconductor devices effects on power density are investigated from the power device figure of merit, high frequency high temperature operation and device parallel operation points of view. / Ph. D.

This dissertation presents the analysis and development of an innovative semiconductor device and topology for the high power current source converter (CSC). The CSC is very attractive in high power applications due to its lower output dv/dt, easy regeneration capability and implicit short-circuit protection. Traditionally, either a symmetrical gate turn-off (GTO) thyritor or an asymmetrical GTO in series with a diode is used as the power switch in the CSC. Since the GTO has a lower switching speed and requires a complicated gate driver, the symmetrical GTO based CSC usually has low dynamic response speed and low efficiency. To achieve high power rating, fast dynamic response speed and low harmonics, an advanced semiconductor device and topology are needed for the CSC. Based on symmetrical GTO and power MOSFET technologies, a symmetrical emitter turn-off (ETO) thyristor is developed that shows superior switching performance, high power rating and reverse voltage blocking capability. The on-state characteristics, forced turn-on characteristics, forced turn-off characteristics and the load-commutated characteristics are studied. Test results show that although the load-commutation loss is high, the developed symmetrical ETO is suitable for use in high power CSC due to its low conduction loss, fast switching speed and reverse voltage blocking capability. The snubberless turn-on capability is preferred for a semiconductor device in a power conversion system, and can be achieved for devices with forward biased safe operation area (FBSOA). The FBSOA of the ETO is investigated and experimentally demonstrated. The ETO device has excellent FBSOA due to the negative feedback provided by the emitter switch. However, the FBSOA for a large area ETO is poor. A new ETO concept is therefore proposed for future development in order to demonstrate the FBSOA over a large area device. To improve the turn-on performance of the large area ETO, a novel concept, named the transistor-mode turn-on, is proposed and studied. During the transistor-mode turn-on process, the ETO behaves like a transistor instead of a thyristor. Without a snubber, the transistor-mode turn-on for the ETO is hard to achieve. Through the selection of a proper gate drive and di/dt snubber, the transistor-mode turn-on can be implemented, and the turn-on performance for the ETO can be dramatically improved. To increase the power rating of the CSC without degrading the utilization of power semiconductor devices, a novel multilevel CSC, named the parallel-cell multilevel CSC, is proposed. Based on a six-switch CSC cell, the parallel-cell multilevel CSC has the advantages of high power rating, low harmonics, fast dynamic response and modularity. Therefore, it is very suitable for high power applications. The power stage design, modeling, control and switching modulation scheme for a parallel-cell multilevel CSC based static var compensator (STATCOM) are analyzed and verified through simulation. / Ph. D.

<div>Power semiconductor devices play an important role in many areas, including household</div><div>appliances, electric vehicles, high speed trains, electric power stations, and renewable energy</div><div>conversion. In the modern era, silicon based devices have dominated the semiconductor</div><div>market, including power electronics, because of their low cost and high performance. The</div><div>applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they</div><div>are nearly reaching fundamental material limits. New wide band gap materials such as silicon</div><div>carbide (SiC) offer significant performance improvements due to superior material properties</div><div>for such applications in and beyond this voltage range. 4H-SiC is a strong candidate</div><div>among other wide band gap materials because of its high critical electric field, high thermal</div><div>conductivity, compatibility with silicon processing techniques, and the availability of high</div><div>quality conductive substrates.</div><div>Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for</div><div>high voltage applications. High blocking voltages require thick drift regions with very light</div><div>doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking</div><div>voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a</div><div>linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved</div><div>through extremely tight process control. In this thesis, we have concluded that superjunction</div><div>devices inevitably have at least some level of charge imbalance which leads to a quadratic</div><div>relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to</div><div>achieve improved performance in the presence of this inevitable imbalance.</div><div>On the other hand, an IGBT combines the benefits of a conductivity modulated drift</div><div>region for significantly reduced specific on-resistance with the voltage controlled input of a</div><div>MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent</div><div>DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This</div><div>is due to the fact that the n+ substrate must be removed to access the p+ collector of the</div><div>IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.</div><div>In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with</div><div>a waffle substrate through simulation, process development, fabrication and characterization.</div><div><div>The waffle substrate would provide the required mechanical support for this class of devices.</div><div>The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm</div><div>.cm², less than half of</div><div>what would be expected without conductivity modulation. An extensive fabrication process</div><div>development for integrating a waffle substrate into an active IGBT structure is described</div><div>in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,</div><div>opening up new applications for SiC power devices.</div></div>

NASA missions require innovative power electronics system and component solutions with long life capability, high radiation tolerance, low mass and volume, and high reliability in space environments. Presently vertical double-diffused MOSFETs (VDMOS) are the most widely used power switching device for space power systems. It is proposed that a new lateral double-diffused MOSFET (LDMOS) designed at UCF can offer improvements in total dose and single event radiation hardness, switching performance, development and manufacturing costs, and total mass of power electronics systems. Availability of a hardened fast-switching power MOSFET will allow space-borne power electronics to approach the current level of terrestrial technology, thereby facilitating the use of more modern digital electronic systems in space. It is believed that the use of a p+/p-epi starting material for the LDMOS will offer better hardness against single-event burnout (SEB) and single-event gate rupture (SEGR) when compared to vertical devices fabricated on an n+/n-epi material. By placing a source contact on the bottom-side of the p+ substrate, much of the hole current generated by a heavy ion strike will flow away from the dielectric gate, thereby reducing electrical stress on the gate and decreasing the likelihood of SEGR. Similarly, the device is hardened against SEB by the redirection of hole current away from the base of the device's parasitic bipolar transistor. Total dose hardness is achieved by the use of a standard complementary metal-oxide semiconductor (CMOS) process that has shown proven hardness against total dose radiation effects.