Al–O monolayers embedded in ultrathin SiO₂ were shown previously to contain Al-induced acceptor states, which capture electrons from adjacent silicon wafers and generate a negative fixed charge that enables efficient Si-surface passivation. Here, we show that this surface passivation is just in part attributed to field-effect passivation, since the electrically active interface trap density Dit itself at the Si/SiO₂ interface is reduced by the presence of the acceptor states. For sufficiently thin tunnel-SiO₂ films between the Si-surface and the Al–O monolayers, Dit is reduced by more than one order of magnitude. This is attributed to an interface defect deactivation mechanism that involves the discharge of the singly-occupied dangling bonds (Pb0 defects) into the acceptor states, so that Shockley-Read-Hall-recombination is drastically reduced. We demonstrate that the combined electronic and field-effect passivation allows for minority carrier lifetimes in excess of 1 ms on n-type Si and that additional H₂-passivation is not able to improve that lifetime significantly.

Ce travail de thèse présente une évaluation approfondie des différentes techniques de mesure transitoire et dynamique pour l’évaluation du comportement électro-thermique des transistors bipolaires à hétérojonctions HBT SiGe:C de la technologie BiCMOS et des transistors Métal-Oxyde-Semiconducteur à effet de champ (MOSFET) de la technologie CMOS 45nm. En particulier, je propose une nouvelle approche pour caractériser avec précision le régime transitoire d'auto-échauffement, basée sur des mesures impulsionelles. La méthodologie a été vérifiée par des mesures statiques à différentes températures ambiantes, des mesures de paramètres S à basses fréquences et des simulations thermiques transitoires. Des simulations thermiques par éléments finis (TCAD) en trois dimensions ont été réalisées sur les transistors HBTs de la technologie submicroniques SiGe: C BiCMOS. Cette technologie est caractérisée par une fréquence de transition fT de 230 GHz et une fréquence maximum d’oscillation fMAX de 290 GHz. Par ailleurs, cette étude a été réalisée sur les différentes géométries de transistor. Une évaluation complète des mécanismes d'auto-échauffement dans les domaines temporels et fréquentiels a été réalisée. Une expression généralisée de l'impédance thermique dans le domaine fréquentiel a été formulée et a été utilisé pour extraire cette impédance en deçà de la fréquence de coupure thermique. Les paramètres thermiques ont été extraits par des simulations compactes grâce au modèle compact de transistors auquel un modèle électro-thermique a été ajouté via le nœud de température. Les travaux théoriques développés à ce jour pour la modélisation d'impédance thermique ont été vérifiés avec nos résultats expérimentaux. Il a été montré que, le réseau thermique classique utilisant un pôle unique n'est pas suffisant pour modéliser avec précision le comportement thermique transitoire et donc qu’un réseau plus complexe doit être utilisé. Ainsi, nous validons expérimentalement pour la première fois, le modèle distribué électrothermique de l'impédance thermique utilisant un réseau nodal récursif. Le réseau récursif a été vérifié par des simulations TCAD, ainsi que par des mesures et celles ci se sont révélées en excellent accord. Par conséquent, un modèle électro-thermique multi-géométries basé sur le réseau récursif a été développé. Le modèle a été vérifié par des simulations numériques ainsi que par des mesures de paramètre S à basse fréquence et finalement la conformité est excellente quelque soit la géométrie des dispositifs. / An extensive evaluation of different techniques for transient and dynamic electro-thermal behavior of microwave SiGe:C BiCMOS hetero-junction bipolar transistors (HBT) and nano-scale metal-oxide-semiconductor field-effect transistors (MOSFETs) have been presented. In particular, new and simple approach to accurately characterize the transient self-heating effect, based on pulse measurements, is demonstrated. The methodology is verified by static measurements at different ambient temperatures, s-parameter measurements at low frequency region and transient thermal simulations. Three dimensional thermal TCAD simulations are performed on different geometries of the submicron SiGe:C BiCMOS HBTs with fT and fmax of 230 GHz and 290 GHz, respectively. A comprehensive evaluation of device self-heating in time and frequency domain has been investigated. A generalized expression for the frequency-domain thermal impedance has been formulated and that is used to extract device thermal impedance below thermal cut-off frequency. The thermal parameters are extracted through transistor compact model simulations connecting electro-thermal network at temperature node. Theoretical works for thermal impedance modeling using different networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the distributed electrothermal model for thermal impedance using a nodal and recursive network. It has been shown that, the conventional single pole thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement. Therefore, finally a scalable electro-thermal model using this recursive network is developed. The scalability has been verified through numerical simulations as well as by low frequency measurements and excellent conformity has been found in for various device geometries.

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

This work presents a 6.5-kV 1-kA SiC bipolar diode module for megawatt-range medium voltage converters. The study comprises a review of SiC devices and bipolar diodes, a description of the die and module technology, device characterization and modelling and benchmark of the device at converter level. The effects of current change rate, temperature variation, and different insulated-gate bipolar transistor (IGBT) modules for the switching cell, as well as parasitic oscillations are discussed. A comparison of the results with a commercial Si diode (6.5 kV and 1.2 kA) is included. The benchmark consists of an estimation of maximum converter output power, maximum switching frequency, losses and efficiency in a three level (3L) neutral point clamped (NPC) voltage-source converter (VSC) operating with SiC and Si diodes. The use of a model predictive control (MPC) algorithm to achieve higher efficiency levels is also discussed. The analysed diode module exhibits a very good performance regarding switching loss reduction, which allows an increase of at least 10 % in the output power of a 6-MVA converter. Alternatively, the switching frequency can be increased by 41 %.

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

Die Anforderungen an schnelle Dioden sind sehr hoch für große Spannungen und große Ströme. Die Beeinflussung des Bauelementverhaltens durch das Design des Dotierprofils mit einem tiefen mehrstufigen Feldstopp aus Selen bildet einen zentralen Punkt der Dissertation. Mit physikalischen Messverfahren werden die in der Literatur nur unzureichend untersuchten Eigenschaften von Selen in Silizium erfasst und als Basis für Bauelementsimulationen verwendet. Für die Untersuchung der Störstelleneigenschaften kommt die klassische aufwändige DLTS zum Einsatz. Des Weiteren werden für diese Untersuchungen die Vorteile der einfacheren frequenzabhängigen Admittanzspektroskopie ausführlich dargelegt. Anhand der Bauelementsimulationen erfolgt ein Vergleich mit Messungen und führt zur Vorstellung und Erläuterung einer verbesserten soften und robusten Diodenstruktur mit tiefen Donatoren aus Selen. / The focus of the following work is the correlation between the field-stop design and the behaviour of high-voltage power diodes. The objective is to present a further improvement of the diode performance using a special field-stop, which optimizes the diode in relation to a soft switching behaviour and an increased robustness. The function of such a field-stop is investigated. Benefits are shown of materials for field-stops with deep impurities in the semiconductor material and of multiple stepped deep field-stop structures. Therefore a central role have silicon diodes with selenium in the field-stop layer. Measurements and simulations with the power device simulator Sentaurus TCAD are done and explain the named correlations. The deep level transient spectroscopy is used as method to analyse the required impurity parameters. Beside this method the evaluation is done by the introduced frequency resolved admittance spectroscopy.

This work presents a 6.5-kV 1-kA SiC bipolar diode module for megawatt-range medium voltage converters. The study comprises a review of SiC devices and bipolar diodes, a description of the die and module technology, device characterization and modelling and benchmark of the device at converter level. The effects of current change rate, temperature variation, and different insulated-gate bipolar transistor (IGBT) modules for the switching cell, as well as parasitic oscillations are discussed. A comparison of the results with a commercial Si diode (6.5 kV and 1.2 kA) is included. The benchmark consists of an estimation of maximum converter output power, maximum switching frequency, losses and efficiency in a three level (3L) neutral point clamped (NPC) voltage-source converter (VSC) operating with SiC and Si diodes. The use of a model predictive control (MPC) algorithm to achieve higher efficiency levels is also discussed. The analysed diode module exhibits a very good performance regarding switching loss reduction, which allows an increase of at least 10 % in the output power of a 6-MVA converter. Alternatively, the switching frequency can be increased by 41 %.:1 Introduction 2 State of the art of SiC devices and medium-voltage diodes 2.1 Silicon carbide diodes and medium-voltage modules 2.2 Medium-voltage power diodes 3 Characterization of the SiC PiN diode module 37 3.1 Introduction 3.2 Experimental setup 3.3 Experimental results: static behaviour 3.4 Experimental results: switching behaviour 3.5 Comparison with 6.5-kV silicon diode 3.6 Oscillations in the SiC diode 3.7 Summary 4 Comparison at converter level 4.1 Introduction 4.2 Power device modelling 4.3 Determination of maximum converter power rating 4.4 Analysis 4.5 Increased efficiency through model predictive control 4.6 Summary 5 Conclusion

Die Anforderungen an schnelle Dioden sind sehr hoch für große Spannungen und große Ströme. Die Beeinflussung des Bauelementverhaltens durch das Design des Dotierprofils mit einem tiefen mehrstufigen Feldstopp aus Selen bildet einen zentralen Punkt der Dissertation. Mit physikalischen Messverfahren werden die in der Literatur nur unzureichend untersuchten Eigenschaften von Selen in Silizium erfasst und als Basis für Bauelementsimulationen verwendet. Für die Untersuchung der Störstelleneigenschaften kommt die klassische aufwändige DLTS zum Einsatz. Des Weiteren werden für diese Untersuchungen die Vorteile der einfacheren frequenzabhängigen Admittanzspektroskopie ausführlich dargelegt. Anhand der Bauelementsimulationen erfolgt ein Vergleich mit Messungen und führt zur Vorstellung und Erläuterung einer verbesserten soften und robusten Diodenstruktur mit tiefen Donatoren aus Selen. / The focus of the following work is the correlation between the field-stop design and the behaviour of high-voltage power diodes. The objective is to present a further improvement of the diode performance using a special field-stop, which optimizes the diode in relation to a soft switching behaviour and an increased robustness. The function of such a field-stop is investigated. Benefits are shown of materials for field-stops with deep impurities in the semiconductor material and of multiple stepped deep field-stop structures. Therefore a central role have silicon diodes with selenium in the field-stop layer. Measurements and simulations with the power device simulator Sentaurus TCAD are done and explain the named correlations. The deep level transient spectroscopy is used as method to analyse the required impurity parameters. Beside this method the evaluation is done by the introduced frequency resolved admittance spectroscopy.

A high-precision mixed-signal mismatch measurement technique for metal-oxide metal (MoM) capacitors as well as the design of a 13-GHz 5-bit 360-degree phase shifter are presented. This thesis presents a high-precision, mixed-signal mismatch measurement technique for metal-oxide–metal capacitors. The proposed technique incorporates a switched-capacitor op amp within the measurement circuit to significantly improve the measurement precision while relaxing the resolution requirement on the backend analog-to-digital converter (ADC). The proposed technique is also robust against multiple types of errors. A detailed analysis is presented to quantify the sensitivity improvement of the proposed technique over the conventional one. In addition, this thesis proposes a multiplexing technique to measure a large number of capacitors in a single chip and a new layout to improve matching. A prototype fabricated in 180 nm CMOS technology demonstrates the ability to sense capacitor mismatch standard deviation as low as 0.045% with excellent repeatability, all without the need of a high-resolution ADC. The 13-GHz 5-bit 360-degree phase shifter consists of 2 stages. The first stage utilizes a delay line for 4-bit 180-degree phase shift. A second stage provides 1-bit 180-degree phase shift. The phase shifter includes gain tuning so as to allow a gain variation of less than 1 dB. The design has been fabricated in 180 nm CMOS technology and measurement results show a complete 360◦ phase shift with an average step size of 10.7◦ at 13-GHz. After calibration the phase shifter presented an output gain S21 of 0.5 dB with a gain variation of less than 1 dB across all codes at 13-GHz. The remaining s-parameter testing showed a S22 and S11 below -11 dB and a S12 below -49 dB at 13 GHz.

Manufacturing process development is under constant pressure to achieve a good yield for stable processes. The development of new technologies, especially in the field of photomask and semiconductor development, is at its phys- ical limits. In this area, data, e.g. sensor data, has to be collected and analyzed for each process in order to ensure process quality. With increasing complexity of manufactur- ing processes, the volume of data that has to be evaluated rises accordingly. The complexity and data volume exceeds the possibility of a manual data analysis. At this point, data mining techniques become interesting. The application of current techniques is complex because most of the data is captured with sensor measurement tools. Therefore, every measured value contains a specific error. In this paper we propose an error-aware extension of the density-based al- gorithm DBSCAN. Furthermore, we present some quality measures which could be utilized for further interpretation of the determined clustering results. With this new cluster algorithm, we can ensure that masks are classified into the correct cluster with respect to the measurement errors, thus ensuring a more likely correlation between the masks.