Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos. / This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.

A utilização de técnicas de tolerância a falhas em software é uma forma de baixo custo para proteger processadores contra soft errors. Contudo, elas causam aumento no tempo de execução e utilização de memória. Em consequência disso, o consumo de energia também aumenta. Sistemas que operam com restrição de tempo ou energia podem ficar impossibilitados de utilizar tais técnicas. Por esse motivo, este trabalho propoe técnicas de tolerância a falhas em software com custos no desempenho e memória reduzidos e cobertura de falhas similar a técnicas presentes na literatura. Como detecção é menos custoso que correção, este trabalho foca em técnicas de detecção. Primeiramente, um conjunto de técnicas de dados baseadas em regras de generalização, chamada VAR, é apresentada. As técnicas são baseadas nesse conjunto generalizado de regras para permitir uma investigação exaustiva, em termos de confiabilidade e custos, de diferentes variações de técnicas. As regras definem como a técnica duplica o código e insere verificadores. Cada técnica usa um diferente conjunto de regras. Então, uma técnica de controle, chamada SETA, é introduzida. Comparando SETA com uma técnica estado-da-arte, SETA é 11.0% mais rápida e ocupa 10.3% menos posições de memória. As técnicas de dados mais promissoras são combinadas com a técnica de controle com o objetivo de proteger tanto os dados quanto o fluxo de controle da aplicação alvo. Para reduzir ainda mais os custos, métodos para aplicar seletivamente as técnicas propostas foram desenvolvidos. Para técnica de dados, em vez de proteger todos os registradores, somente um conjunto de registradores selecionados é protegido. O conjunto é selecionado com base em uma métrica que analisa o código e classifica os registradores por sua criticalidade. Para técnicas de controle, há duas abordagens: (1) remover verificadores de blocos básicos, e (2) seletivamente proteger blocos básicos. As técnicas e suas versões seletivas são avaliadas em termos de tempo de execução, tamanho do código, cobertura de falhas, e o Mean Work to Failure (MWTF), o qual é uma métrica que mede o compromisso entre cobertura de falhas e tempo de execução. Resultados mostram redução dos custos sem diminuição da cobertura de falhas, e para uma pequena redução na cobertura de falhas foi possível significativamente reduzir os custos. Por fim, uma vez que a avaliação de todas as possíveis combinações utilizando métodos seletivos toma muito tempo, este trabalho utiliza um método para extrapolar os resultados obtidos por simulação com o objetivo de encontrar os melhores parâmetros para a proteção seletiva e combinada de técnicas de dados e de controle que melhorem o compromisso entre confiabilidade e custos. / Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code size, which consequently increases the energy consumption. System operation with time or energy restrictions may not be able to make use of these techniques. For this reason, this work proposes software-based fault tolerance techniques with lower overheads and similar fault coverage to state-of-the-art software techniques. Once detection is less costly than correction, the work focuses on software-based detection techniques. Firstly, a set of data-flow techniques called VAR is proposed. The techniques are based on general building rules to allow an exhaustive assessment, in terms of reliability and overheads, of different technique variations. The rules define how the technique duplicates the code and insert checkers. Each technique uses a different set of rules. Then, a control-flow technique called SETA (Software-only Error-detection Technique using Assertions) is introduced. Comparing SETA with a state-of-the-art technique, SETA is 11.0% faster and occupies 10.3% fewer memory positions. The most promising data-flow techniques are combined with the control-flow technique in order to protect both dataflow and control-flow of the target application. To go even further with the reduction of the overheads, methods to selective apply the proposed software techniques have been developed. For the data-flow techniques, instead of protecting all registers, only a set of selected registers is protected. The set is selected based on a metric that analyzes the code and rank the registers by their criticality. For the control-flow technique, two approaches are taken: (1) removing checkers from basic blocks: all the basic blocks are protected by SETA, but only selected basic blocks have checkers inserted, and (2) selectively protecting basic blocks: only a set of basic blocks is protected. The techniques and their selective versions are evaluated in terms of execution time, code size, fault coverage, and Mean Work To Failure (MWTF), which is a metric to measure the trade-off between fault coverage and execution time. Results show that was possible to reduce the overheads without affecting the fault coverage, and for a small reduction in the fault coverage it was possible to significantly reduce the overheads. Lastly, since the evaluation of all the possible combinations for selective hardening of every application takes too much time, this work uses a method to extrapolate the results obtained by simulation in order to find the parameters for the selective combination of data and control-flow techniques that are probably the best candidates to improve the trade-off between reliability and overheads.

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada. / Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que exigem um baixo consumo de área e energia e boa velocidade de conversão. Esta topologia está presente em diversos dispositivos programáveis comerciais, como também em circuitos integrados de propósito geral. Tais dispositivos, quando expostos a ambientes suscetíveis a radiação, como é o caso de aplicações espaciais, estão sujeitos à colisão com partículas capazes de ionizar o silício. Estes podem causar falhas temporárias, como um efeito transiente, uma inversão de bit em um elemento de memória, ou até mesmo danos permanentes no circuito. Este trabalho visa descrever o comportamento do conversor SAR baseado em redistribuição de carga após a ocorrência de efeitos transientes causados por radiação, por meio de simulação SPICE. Tais efeitos podem causar falhas nos componentes da topologia: chaves, lógica de controle e comparador. Estes são propagados por todo o estágio de conversão, devido à sua característica sequencial de conversão. Por fim, uma discussão sobre as possíveis técnicas de mitigação de falhas para esta topologia é apresentada. / Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) based on charge redistribution are frequently used in data acquisition systems, especially those requiring low power and low area, and good conversion speed. This topology is present on several mixed-signal programmable devices. These devices, when exposed to harsh environments, such as radiation, which is the case for space applications, are prone to Single Event Effects (SEEs). These effects may cause temporary failures, such as transient effects or memory upsets or even permanent failures on the circuit. This work presents the behavior of this type of converter after the occurrence of a transient fault on the circuit, by means of SPICE simulations. These transient faults may cause an inversion on the conversion due to a transient on the control logic of the switches, or a charge or discharge of the capacitors when a transient occur on the switches, as well as a failure on the comparator, which may propagate to the remainder stages of conversion, due to the sequential nature of the converter. A discussion about the possible fault mitigation techniques is also presented.

This master thesis discuss about ionizing radiation, interaction with matter and effects on her. In the work is discussed differend types of interactions of directly ionizing radiation and indirectly ionizing radiation. Below is an overview of methods of shielding from all of types of ionizing radiation. Second part of this thesis discuss about single event effects in semiconductors which are cause by ionizing radiation. At the end is described design of measuring instrument included FPGA chips. This design is discused both from point of wiew hardware and software too.

This master thesis discuss about ionizing radiation, interaction with matter and effects on her. In the work is discussed differend types of interactions of directly ionizing radiation and indirectly ionizing radiation. Below is an overview of methods of shielding from all of types of ionizing radiation. Second part of this thesis discuss about single event effects in semiconductors which are cause by ionizing radiation. At the end is described design of measuring instrument included FPGA chips. This design is discused both from point of wiew hardware and software too.

The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..

This thesis evaluates the suitability of silicon-germanium technology for electronic systems intended for extreme environments, such as ambient temperatures outside of military specification (-55 degC to 125 degC) range and intense exposures to ionizing radiation. Silicon-germanium devices and circuits were characterized at cryogenic and high-temperatures (up to 300 degC) and exposed to ionizing radiation, providing empirical evidence that silicon-germanium is an excellent platform for terrestrial and space-based electronic applications.

L'objectif principal de cette thèse est de développer des techniques d'analyse et mitigation capables à contrer les effets des Evènements Singuliers (Single Event Effects) - perturbations externes et internes produites par les particules radioactives, affectant la fiabilité et la sureté en fonctionnement des circuits microélectroniques complexes. Cette thèse à la vocation d'offrir des solutions et méthodologies industrielles pour les domaines d'applications terrestres exigeant une fiabilité ultime (télécommunications, dispositifs médicaux, ...) en complément des travaux précédents sur les Soft Errors, traditionnellement orientés vers les applications aérospatiales, nucléaires et militaires.Les travaux présentés utilisent une décomposition de sources d'erreurs dans les circuits actuels, visant à mettre en évidence les contributeurs les plus importants.Les upsets (SEU) - Evènements Singuliers (ES) dans les cellules logiques séquentielles représentent actuellement la cible principale pour les efforts d'analyse et d'amélioration à la fois dans l'industrie et dans l'académie. Cette thèse présente une méthodologie d'analyse basée sur la prise en compte de la sensibilité de chaque état logique d'une cellule (state-awareness), approche qui améliore considérablement la précision des résultats concernant les taux des évènements pour les instances séquentielles individuelles. En outre, le déséquilibre intrinsèque entre la susceptibilité des différents états des bascules est exploité pour mettre en œuvre une stratégie d'amélioration SER à très faible coût.Les fautes transitoires (SET) affectant la logique combinatoire sont beaucoup plus difficiles à modéliser, à simuler et à analyser que les SEUs. L'environnement radiatif peut provoquer une multitude d'impulsions transitoires dans les divers types de cellules qui sont utilisés en configurations multiples. Cette thèse présente une approche pratique pour l'analyse SET, applicable à des circuits industriels très complexes. Les principales étapes de ce processus consiste à: a) caractériser complètement la bibliothèque de cellules standard, b) évaluer les SET dans les réseaux logiques du circuit en utilisant des méthodes statiques et dynamiques et c) calculer le taux SET global en prenant en compte les particularités de l'implémentation du circuit et de son environnement.L'injection de fautes reste la principale méthode d'analyse pour étudier l'impact des fautes, erreurs et disfonctionnements causés par les évènements singuliers. Ce document présente les résultats d'une analyse fonctionnelle d'un processeur complexe dans la présence des fautes et pour une sélection d'applications (benchmarks) représentatifs. Des techniques d'accélération de la simulation (calculs probabilistes, clustering, simulations parallèles) ont été proposées et évalués afin d'élaborer un environnement de validation industriel, capable à prendre en compte des circuits très complexes. Les résultats obtenus ont permis l'élaboration et l'évaluation d'un hypothétique scénario de mitigation qui vise à améliorer sensiblement, et cela au moindre coût, la fiabilité du circuit sous test. Les résultats obtenus montrent que les taux d'erreur, SDC (Silent Data Corruption) et DUE (Detectable Uncorrectable Errors) peuvent être considérablement réduits par le durcissement d'un petite partie du circuit (protection sélective). D'autres techniques spécifiques ont été également déployées: mitigation du taux de soft-errors des Flip-Flips grâce à une optimisation du Temporal De-Rating par l'insertion sélective de retard sur l'entrée ou la sortie des bascules et biasing du circuit pour privilégier les états moins sensibles.Les méthodologies, algorithmes et outils CAO proposés et validés dans le cadre de ces travaux sont destinés à un usage industriel et ont été valorisés dans le cadre de plateforme CAO commerciale visant à offrir une solution complète pour l'évaluation de la fiabilité des circuits et systèmes électroniques complexes. / The main objective of this thesis is to develop analysis and mitigation techniques that can be used to face the effects of radiation-induced soft errors - external and internal disturbances produced by radioactive particles, affecting the reliability and safety in operation complex microelectronic circuits. This thesis aims to provide industrial solutions and methodologies for the areas of terrestrial applications requiring ultimate reliability (telecommunications, medical devices, ...) to complement previous work on Soft Errors traditionally oriented aerospace, nuclear and military applications.The work presented uses a decomposition of the error sources, inside the current circuits, to highlight the most important contributors.Single Event Effects in sequential logic cells represent the current target for analysis and improvement efforts in both industry and academia. This thesis presents a state-aware analysis methodology that improves the accuracy of Soft Error Rate data for individual sequential instances based on the circuit and application. Furthermore, the intrinsic imbalance between the SEU susceptibility of different flip-flop states is exploited to implement a low-cost SER improvement strategy.Single Event Transients affecting combinational logic are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The working environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. This thesis presents practical approach to a possible exhaustive Single Event Transient evaluation flow in an industrial setting. The main steps of this process consists in: a) fully characterize the standard cell library using a process and library-aware SER tool, b) evaluate SET effects in the logic networks of the circuit using a variety dynamic (simulation-based) and static (probabilistic) methods and c) compute overall SET figures taking into account the particularities of the implementation of the circuit and its environment.Fault-injection remains the primary method for analyzing the effects of soft errors. This document presents the results of functional analysis of a complex CPU. Three representative benchmarks were considered for this analysis. Accelerated simulation techniques (probabilistic calculations, clustering, parallel simulations) have been proposed and evaluated in order to develop an industrial validation environment, able to take into account very complex circuits. The results obtained allowed the development and evaluation of a hypothetical mitigation scenario that aims to significantly improve the reliability of the circuit at the lowest cost.The results obtained show that the error rate, SDC (Silent Data Corruption) and DUE (Detectable Uncorrectable Errors) can be significantly reduced by hardening a small part of the circuit (Selective mitigation).In addition to the main axis of research, some tangential topics were studied in collaboration with other teams. One of these consisted in the study of a technique for the mitigation of flip-flop soft-errors through an optimization of the Temporal De-Rating (TDR) by selectively inserting delay on the input or output of flip-flops.The Methodologies, the algorithms and the CAD tools proposed and validated as part of the work are intended for industrial use and have been included in a commercial CAD framework that offers a complete solution for assessing the reliability of circuits and complex electronic systems.

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.