Se a música brasileira em muitas de suas manifestações é reconhecida pela sua excelência, o mesmo não se pode dizer dos instrumentos musicais produzidos em território nacional. Em relação aos instrumentos eletrônicos que começaram a surgir na década de 1960, isso leva a crer que não houve nenhuma iniciativa dentro do Brasil que pudesse mudar esse quadro. No entanto, isto está longe de ser verdade, como esta pesquisa pretende mostrar. Mesmo assim, até hoje a confecção de instrumentos eletrônicos é dominada pela indústria estrangeira, sugerindo uma maior investigação e reflexão dos fatores que levaram a esta situação. Como será visto, isto não tem a ver somente com a qualidade (ou falta dela) dos projetos descritos ao longo desta pesquisa, mas com outros fatores que vão para além de problemas meramente tecnológicos ou musicais. / If Brazilian music in its various manifestations is recognized as excellent, it cant be said the same about the musical instruments made in the country. Regarding the electronic musical instruments that began to be made about the 1960s onwards, this lead to the believing that nothing was made inside the country to change that scene. But it is far from true, and that is the point of this text. Otherwise, the making of electronic musical instruments is dominated by a foreign industry, suggesting a broader investigation and reflection about the facts that led to this situation. As it will be seen, this has nothing to do with the quality (or the lackof it) of the projects described along this text, but with other reasons going beyond questions simply put as technological or musical.

Mina erfarenheter av att ha skapat musik både med mjukvarusyntar och genom att komponera för akustiska instrument har lett till idén om att tillämpa uttrycksfullheten hos akustiska instrument på mjukvarusyntar.   Syftet med arbetet är att undersöka hur jag kan få mjukvarusyntar att låta musikaliskt uttrycksfulla genom att tillämpa de uttrycksparametrar som används vid spel på akustiska instrument. Frågeställningarna är:   Hur kan jag definiera faktorerna bakom uttrycksfullheten hos akustiska instrument i form av ett antal uttrycksparametrar?   Hur kan jag tillämpa dessa uttrycksparametrar vid programmering av nya patcher i mjukvarusyntar?   Vilka egenskaper hos en mjukvarusynt är önskvärda när man vill tillämpa uttrycksparametrarna?   Vilka skillnader i uttrycksfullhet upplever jag om jag jämför ett arrangemang för mjukvarusyntar av ett musikstycke med ett arrangemang för akustiska instrument av samma stycke?   I arbetets genomförande definierar jag ovan nämnda uttrycksparametrar. Jag undersöker tillämpningen av dessa genom att arrangera ett befintligt pianostycke för tre olika mjukvarusyntar i Logic Pro. Jag jämför sedan uttrycksfullheten i mitt arrangemang och i ett arrangemang för akustiska instrument.   Genom arbetet har jag kommit en bit på vägen till att få mjukvarusyntar att låta uttrycksfulla på akustiska instruments vis. Jag tror att man skulle kunna dra nytta av musikakustik för att nå längre.

Syftet med den här studien är att bryta ner och beskriva processen om hur man skapar olika typer av ljud på en synthesizer. Underlaget för studien har varit böcker, videor och praktiskt erfarenhet. För att få praktisk erfarenhet har jag arbetat med att göra soundalikes av sammanlagt fyra poplåtar. Låtarna representerar fyra olika decennier och innehåller typiska syntljud för sin tid. Resultatet mynnade ut i en mall där det beskrivs hur man med fem steg kommer fram till nästan vilket ljud som helst.

<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sources which cannot be switched on simultaneously and have equal weights are shared. After sharing weights, the control signals are reduced to from 59 to 43 and current sources from 207 to 145.</p><p>Different control words are used by the DDFS system in order to generate different frequencies. The control word is successively added to the previous value in a 20-bit accumulator. Nine most significant bits out of these twenty bits are used for the DAC.</p><p>Since the Current Steering DAC architecture is suitable for high speed and high resolution purposes, so a 9-bit nonlinear current steering DAC is used to convert the output of bit products to the analog sine wave. Seven bits are used to generate one quarter of the sine wave. Eighth and ninth bits are used to generate the full sine wave.</p><p>HCMOS 9 (130 nm) ST Microelectronics process is used by employing high speed NMOS and PMOS transistors. The bit products (control signals) are computed by using complementary static CMOS logic which then act as control signals for the current sources after passing through D-flip flops. Practical design issues of current sources and parts of digital logic were studied and implemented using the Cadence full-custom design environment.</p>

The Akai EWI4000s is the most recent model of the EWI (Electric Wind Instrument) family, first conceived by Nyle Steiner in the late 1970’s. A relatively young electronic instrument, the EWI lacks a complete, organized publication explaining how to fully utilize its technical and expressive devices. Furthermore, no instructional aid exists to explain the parameters of the Vyzex computer editor used to create and manipulate the onboard sound bank of the EWI4000s. The purpose of this study is to inform the reader of how the EWI4000s came to fruition, to develop a complete technical and expressive method for learning to play the EWI4000s, and to create a musically based manual for using the Vyzex computer editor. Using text, diagrams, and musical examples, the method acquaints the reader with the EWI’s internal and external controls by explaining their functions using musical terms easily understood by the common musician. Additionally, new notation is created to constrain the EWI’s seven-octave range exclusively within the treble clef staff making it easier to compose and read EWI music without excessive clef changes and musical octave markings. The new notation also develops symbols to dictate use of the EWI’s expressive devices such as pitch bend, glissando, octave doubling, and harmonization.

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.

The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR). The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip¡¦s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2.