Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2017-11-13T21:02:54Z No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-11-21T12:14:27Z (GMT) No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) / Made available in DSpace on 2017-11-21T12:26:58Z (GMT). No. of bitstreams: 1 Felipe_Gohring_de_Magalh?es_TES.pdf: 7728697 bytes, checksum: f2b34275e49f32253d8c38848a3d9258 (MD5) Previous issue date: 2017-05-25 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior - CAPES / As tend?ncias de design para os sistemas multiprocessadores da pr?xima gera??o apontam para a integra??o de um grande n?mero de n?cleos de processamento, exigindo interconex?es de alto desempenho. Uma solu??o a ser aplicada para melhorar a infraestrutura de comunica??o em tais sistemas ? o uso de redes on-chip, pois estas apresentam uma melhoria consider?vel na largura de banda e escalabilidade. Ainda assim, o n?mero de n?cleos integrados continua a aumentar ao mesmo tempo em que o sistema cresce, dessa maneira as interconex?es met?licas em redes on-chip podem tornar-se um gargalo no desempenho. Como resultado, uma nova estrat?gia deve ser adotada para que essas quest?es sejam solucionadas. As Redes ?pticas Integradas (do ingl?s Optical Integrated Networks - OINs) s?o atualmente consideradas como um dos paradigmas mais promissores neste contexto de design: elas apresentam maior largura de banda, menor consumo de energia e baixa lat?ncia para transmitir informa??es. Al?m disso, trabalho recentes demonstram a viabilidade de OINs com suas tecnologias de fabrica??o dispon?veis e compat?veis com CMOS. No entanto, os designers de OINs enfrentam v?rios desafios: ? Atualmente, os controladores representam o principal gargalo na comunica??o e s?o um dos fatores que limitam o uso de OINs. Portanto, novas solu??es de controle de baixa lat?ncia s?o necess?rias. ? Designers n?o possuem ferramentas para modelar e validar OINs. A maioria das pesquisas atualmente est? focada em projetar dispositivos e melhorar os componentes b?sicos, deixando o sistema sem melhorias. Neste contexto, para facilitar a implanta??o de sistemas baseados em OIN, este projeto de doutorado concentra-se em tr?s contribui??es principais: (1) o desenvolvimento da plataforma de simula??o a n?vel de sistema; (2) a defini??o e o desenvolvimento de uma abordagem de controle eficiente para sistemas baseados em OIN e; (3) a avalia??o, a n?vel do sistema, da abordagem de controle proposta usando a modelagem definida. / Design trends for next-generation Multi-Processor Systems point to the integration of a large number of processing cores, requiring high-performance interconnects. One solution being applied to improve the communication infrastructure in such systems is the usage of Networkson- Chip as they present considerable improvement in the bandwidth and scaleability. Still as the number of integrated cores continues to increase and the system scales, the metallic interconnects in Networks-on-Chip can become a performance bottleneck. As a result, a new strategy must be adopted in order for those issues to be remedied. Optical Integrated Networks (OINs) are currently considered to be one of the most promising paradigm in this design context: they present higher bandwidth, lower power consumption and lower latency to broadcast information. Also, the latest work demonstrates the feasibility of OINs with their fabrication technologies being available and CMOS compatible. However, OINs? designers face several challenges: ? Currently, controllers represent the main communication bottleneck and are one of the factors limiting the usage of OINs. Therefore, new controlling solutions with low latency are required. ? Designers lack tools to model and validate OINs. Most research nowadays is focused on designing devices and improving basic components performance, leaving system unattended. In this context, in order to ease the deployment of OIN-based systems, this PhD project focuses on three main contributions: (1) the development of accurate system-level modelling study to realize a system-level simulation platform; (2) the definition and development of an efficient control approach for OIN-based systems, and; (3) the system-level evaluation of the proposed control approach using the defined modelling.

L'augmentation de la densité des transistors dans les circuits électroniques conduit à une augmentation de la consommation d'énergie induisant des phénomènes thermiques plus complexes à maitriser. Dans le cas de systèmes embarqués en environnement où la température ambiante varie dans des proportions importantes (automobile par exemple), ces phénomènes peuvent conduire à des problèmes de fiabilité. Parmi les mécanismes de défaillance observés, on peut citer les cycles thermiques (CT) qui induisent des déformations dans les couches métalliques de la puce pouvant conduire à des fissurations. L’objectif de la thèse est de proposer pour des architectures de type multiprocesseur sur puce une technique de réduction des CT subis par les processeurs, et ce en respectant les contraintes temps réel des applications. L’exemple du circuit MPC5517 de Freescale a été considéré. Dans un premier temps un modèle thermique de ce circuit a été élaboré à partir de mesures par une caméra thermique sur ce circuit décapsulé. Un environnement de simulation a été mis en oeuvre pour permettre d’effectuer simultanément des analyses thermiques et d’ordonnancement de tâches et mettre en évidence l’influence de la température sur la puissance dissipée. Une heuristique globale pour réduire à la fois les CT et la température maximale des processeurs a été étudiée. Elle tient compte des variations de la température ambiante et se base sur les techniques DVFS et DPM. Les résultats de simulation avec les algorithmes d’ordonnancement globaux RM, EDF et EDZL et avec différentes charges processeur (sur un circuit type MPC5517 et un UltraSparc T1) illustrent l’efficacité de la technique proposée. / Increasing the density of transistors in electronic circuits leads to an increase in energy consumption resulting in more complex thermal phenomena to master. For systems embedded in environments where the ambient temperature can vary in large range (e.g. automotive), these thermal effects can induce reliability problems. Among classical failure mechanisms thermal cycles (CTs) produce deformations in materials and play a major role in the cracking of the metal layers in the chip. The aim of the thesis is to propose a reduction technique of CTs suffered by the processor cores in a multiprocessor on chip architecture such that real-time application constraints are met. The example of the Freescale MPC5517 circuit has been considered. In a first step a thermal model of this circuit was developed. This was achieved from measurements taken by a thermal camera on a decapsulated circuit. Next, a simulation environment has been implemented allowing both the analysis of thermal behavior and the scheduling of tasks so as to highlight the influence of temperature on the dissipated power. A global heuristic to reduce both the CTs and the maximum temperature of processors has been studied. It takes into account variations in the ambient temperature and is based on DVFS and DPM techniques. Simulation results with global scheduling algorithms RM, EDF and EDZL and different processor loads (for a MPC5517 type circuit and a T1 UltraSparc from Sun Microsystems) illustrate the effectiveness of the proposed technique.

The Internet of Things (IoT) has ushered in an age where low-power sensors generate data which are communicated to a back-end cloud for massive data computation tasks. From the hardware perspective this implies co-existence of several power-efficient sub-systems working harmoniously at the sensor nodes capable of communication and high-speed processors in the cloud back-end. The package-board system-level design plays a crucial role in determining the performance of such low-power sensors and high-speed computing and communication systems. Although there exist several commercial solutions for electromagnetic and circuit analysis and verification, problem diagnosis and design tools are lacking leading to longer design cycles and non-optimal system designs. This work aims at developing methodologies for faster analysis, sensitivity based diagnosis and multi-objective design towards signal integrity and power integrity of such package-board system layouts. The first part of this work aims at developing a methodology to enable faster and more exhaustive design space analysis. Electromagnetic analysis of packages and boards can be performed in time domain, resulting in metrics like eye-height/width and in frequency domain resulting in metrics like s-parameters and z-parameters. The generation of eye-height/width at higher bit error rates require longer bit sequences in time domain circuit simulation, which is compute-time intensive. This work explores learning based modelling techniques that rapidly map relevant frequency domain metrics like differential insertion-loss and cross-talk, to eye-height/width therefore facilitating a full-factorial design space sweep. Numerical results performed with artificial neural network as well as least square support vector machine on SATA 3.0 and PCIe Gen 3 interfaces generate less than 2% average error with order of magnitude speed-up in eye-height/width computation. Accurate power distribution network design is crucial for low-power sensors as well as a cloud sever boards that require multiple power level supplies. Achieving target power-ground noise levels for low power complex power distribution networks require several design and analysis cycles. Although various classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools is limited. In the second part of the thesis, a frequency domain mesh-based sensitivity formulation for DC and AC impedance (z-parameters) is proposed. This formulation enables diagnosis of layout for maximum impact in achieving target specifications. This sensitivity information is also used for linear approximation of impedance profile updates for small mesh variations, enabling faster analysis. To enable designing of power delivery networks for achieving target impedance, a mesh-based decoupling capacitor sensitivity formulation is presented. Such an analytical gradient is used in gradient based optimization techniques to achieve an optimal set of decoupling capacitors with appropriate values and placement information in package/boards, for a given target impedance profile. Gradient based techniques are far less expensive than the state of the art evolutionary optimization techniques used presently for a decoupling capacitor network design. In the last part of this work, the functional similarities between package-board design and radio frequency imaging are explored. Qualitative inverse-solution methods common to the radio frequency imaging community, like Tikhonov regularization and Landweber methods are applied to solve multi-objective, multi-variable signal integrity package design problems. Consequently a novel Hierarchical Search Linear Back Projection algorithm is developed for an efficient solution in the design space using piecewise linear approximations. The presented algorithm is demonstrated to converge to the desired signal integrity specifications with minimum full wave 3D solve iterations.

Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA. / <p>QC 20140609</p>