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Embedded systems have become indispensable in our life: household appliances, cars, airplanes, power plant control systems, medical equipment, telecommunication systems, space technology, they all contain digital computing systems with dedicated functionality. Most of them, if not all, are real-time systems, i.e. their responses to stimuli have timeliness constraints. The timeliness requirement has to be met despite some unpredictable, stochastic behaviour of the system. In this thesis, we address two causes of such stochastic behaviour: the application and platform-dependent stochastic task execution times, and the platform-dependent occurrence of transient faults on network links in networks-on-chip. We present three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each of the three approaches fits best to a different context. The first approach is an exact one and is efficiently applicable to monoprocessor systems. The second approach is an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed. It is efficiently applicable to multiprocessor systems. The third approach is less accurate but sufficiently fast in order to be placed inside optimisation loops. Based on the last approach, we propose a heuristic for task mapping and priority assignment for deadline miss ratio minimisation. Our contribution is manifold in the area of buffer and time constrained communication along unreliable on-chip links. First, we introduce the concept of communication supports, an intelligent combination between spatially and temporally redundant communication. We provide a method for constructing a sufficiently varied pool of alternative communication supports for each message. Second, we propose a heuristic for exploring the space of communication support candidates such that the task response times are minimised. The resulting time slack can be exploited by means of voltage and/or frequency scaling for communication energy reduction. Third, we introduce an algorithm for the worst-case analysis of the buffer space demand of applications implemented on networks-on-chip. Last, we propose an algorithm for communication mapping and packet timing for buffer space demand minimisation. All our contributions are supported by sets of experimental results obtained from both synthetic and real-world applications of industrial size.

The fields of System-On-Chip (SOC) and Embedded Systems Design have received a lot of attention in the last years. As part of an effort to increase productivity and reduce the time-to-market of new products, different approaches for Electronic System-Level Design frameworks have been proposed. These different methods promise a transparent co-design of hardware and software without having to focus on the final hardware/software split. In our work, we focused on enhancing the component database, modeling and synthesis capabilities of the System-On-Chip Environment (SCE). We investigated two different virtual platform emulators (QEMU and OVP) for integration into SCE. Based on a comparative analysis, we opted on integrating the Open Virtual Platforms (OVP) models and tested the enhanced SCE simulation, design and synthesis capabilities with a JPEG encoder application, which uses both custom hardware and software as part of the system. Our approach proves not only to provide fast functional verification support for designers (10+ times faster than cycle accurate models), but also to offer a good speed/accuracy relationship when compared against integration of cycle accurate or behavioral (host-compiled) models. / text

This Master of Science Thesis contains the result of a product development project, conducted in collaboration with Scania CV AB in Södertälje. Scania has a successful history in vehicle modularization and therefore wanted to investigate the possibility to modularize their test rigs as well, in order to gain various types of benefits. The section UTT (Laboratory Technology) at Scania, where the project was conducted, had however little experience in product modularization. The author of the thesis therefore identified a specific test rig and modularized it by using appropriate methods. Moreover, a new method was developed by the author, in order to modularize the test rig according to both product complexity and company strategies. This was done by adapting the DSM (Design Structure Matrix) with strategies from the MIM (Module Indication Matrix), before clustering it with the IGTA++ clustering algorithm. The result of the different modularization methods was finally evaluated and compared, before choosing the most suitable modular test rig architecture. The chosen architecture was then analyzed, in order to determine potential benefits that it could offer. Another purpose of the thesis was to answer the research questions about the possibility to combine a DSM and MIM, and if that would improve the result when modularizing a product. The thesis also aimed at providing the project owners with a theoretical background in the field of product modularization and System-Level design (embodiment design). The conclusions of the thesis is that the chosen modular test rig architecture has 41% less complexity (compared with the original architecture) and could potentially increase the flexibility, reduce the risk of design mistakes and reduce the development time by up to 70%. It would also be theoretically possible to reuse up to 57% of the modules, when redesigning the test rig in the future. The thesis also identified that it is possible to transfer some information from a MIM and import it to a DSM, which answered one of the research questions, it was however not possible to claim that it will always improve the result. / Detta M.Sc. examensarbete innehåller resultatet av ett produktframtagningsprojekt som genomfördes i samarbete med Scania CV AB i Södertälje. Scania har en framgångsrik historia inom modularisering av fordon och var därför intresserade av att undersöka möjligheten att modularisera sina provningsriggar, för att uppnå olika typer av strategiska fördelar. Sektionen UTT (Laboratorieteknik) på Scania, där projektet genomfördes, hade dock lite erfarenhet av modularisering av produkter. Författaren av detta examensarbete identifierade därför en specifik provningsrigg och modulariserade den med hjälp av lämpliga metoder. Dessutom utvecklades en ny metod av författaren för att både kunna betrakta företagsstrategier och produktkomplexiteten under modulariseringen. Detta gjordes genom att anpassa en DSM (Design Structure Matrix) med strategier från en MIM (Module Indication Matrix), innan den klustrades med hjälp av algoritmen IGTA++. Resultatet av de olika modulariseringsmetoderna utvärderades och jämfördes slutligen innan den lämpligaste modulära provriggsarkitekturen valdes. Den valda arkitekturen analyserades sedan för att identifiera tänkbara strategiska fördelar som den skulle kunna möjliggöra. Ett annat syfte med examensarbetet var att besvara forskningsfrågorna om möjligheten att kombinera en DSM och MIM, och om det i så fall skulle förbättra resultatet av modulariseringen. Målet med examensarbetet var också att förse sektionen UTT med en teoretisk bakgrund inom modularisering och systemkonstruktion. Slutsatserna av examensarbetet är att den valda modulära produktarkitekturen har 41% lägre komplexitet (jämfört med den ursprungliga arkitekturen) och skulle dessutom potentiellt kunna öka flexibiliteten, minska risken för konstruktionsfel samt minska ledtiden (under utvecklingen) med upp till 70%. Det skulle också vara teoretiskt möjligt att återanvända upp till 57% av modulerna när den studerade provningsriggen behöver utvecklas i framtiden. Under examensarbetet identifierades också möjligheten att överföra information från en MIM till en DSM, vilket besvarade en av forskningsfrågorna. Det var dock inte möjligt att besvara frågan om det alltid förbättrar resultatet.

The work presented in this thesis targets the analysis and implementation of multi-criteria performance prediction methods for System-on-Chips (SoC).<p>These new SoC architectures offer the opportunity to integrate complete heterogeneous systems into a single chip and can be used to design battery powered handhelds, security critical systems, consumer electronics devices, etc. However, this variety in terms of application usually comes with a lot of different performance objectives like power consumption, yield, design cost, production cost, silicon area and many others. These performance requirements are often very difficult to meet together so that SoC design usually relies on making the right design choices and finding the best performance compromises.<p>In parallel with this architectural paradigm shift, new Very Deep Submicron (VDSM) silicon processes have more and more impact on the performances and deeply modify the way a VLSI system is designed even at the first stages of a design flow.<p>In such a context where many new technological and system related variables enter the game, early exploration of the impact of design choices becomes crucial to estimate the performance of the system to design and reduce its time-to-market.<p>In this context, this thesis presents: <p>- A study of state-of-the-art tools and methods used to estimate the performances of VLSI systems and an original classification based on several features and concepts that they use. Based on this comparison, we highlight their weaknesses and lacks to identify new opportunities in performance prediction.<p>- The definition of new concepts to enable the automatic exploration of large design spaces based on flexible performance criteria and degrees of freedom representing design choices.<p>- The implementation of a couple of two new tools of our own:<p>- Nessie, a tool enabling hierarchical representation of an application along with its platform and automatically performs the mapping and the estimation of their performance.<p>-Yeti, a C++ library enabling the defintion and value estimation of closed-formed expressions and table-based relations. It provides the user with input and model sensitivity analysis capability, simulation scripting, run-time building and automatic plotting of the results. Additionally, Yeti can work in standalone mode to provide the user with an independent framework for model estimation and analysis.<p><p>To demonstrate the use and interest of these tools, we provide in this thesis several case studies whose results are discussed and compared with the literature.<p>Using Yeti, we successfully reproduced the results of a model estimating multi-core computation power and extended them thanks to the representation flexibility of our tool.<p>We also built several models from the ground up to help the dimensioning of interconnect links and clock frequency optimization.<p>Thanks to Nessie, we were able to reproduce the NoC power consumption results of an H.264/AVC decoding application running on a multicore platform. These results were then extended to the case of a 3D die stacked architecture and the performance benefits are then discussed.<p>We end up by highlighting the advantages of our technique and discuss future opportunities for performance prediction tools to explore. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished

The United States Navy is committed to developing technology for an All-Electric Ship (AES) that promises to improve the affordability and capability of its next-generation warships. With the addition of power-intensive 21st century electrical systems, future thermal loads are projected to exceed current heat removal capacity. Furthermore, rising fuel costs necessitate a careful approach to total-ship energy management. Accordingly, the aim of this research is to develop computer tools for early-stage design of shipboard energy distribution systems. A system-level model is developed that enables ship designers to assess the effects of thermal and electrical system configurations on fuel efficiency and survivability. System-level optimization and design exploration, based on these energy system models, is challenging because the models are sometimes computationally expensive and characterized by discrete design variables and discontinuous responses. To address this challenge, a classifier-guided sampling (CGS) method is developed that uses a Bayesian classifier to pursue solutions with desirable performance characteristics. The CGS method is tested on a set of example problems and applied to the AES energy system model. Results show that the CGS method significantly improves the rate of convergence towards known global optima, on average, when compared to genetic algorithms. / text

The current trend in embedded systems design is to move the initial design and exploration phase to a higher level of abstraction, in order to tackle the rapidly increasing complexity of embedded systems. One approach of abstracting software development from the low level platform details is host- compiled simulation. Characteristics of the target platform are represented in a host-compiled simulation model by annotating the high level source code. Compiler optimizations make accurate annotation of the code a challenging task. In this thesis, we describe an approach to enable correct back-annotation of C code at the basic block level, while taking compiler optimizations into account. / text

Les nouveaux besoins en communications sans fil pussent le développement de systèmes de transmission RF en termes the reconfigurabilité, multistandard et à basse consommation. Ces travaux de thèse font l’objet de la proposition d’une nouvelle architecture de réception capable d’adresser ces aspects dans le contexte des réseaux WPAN. La technique de sous échantillonnage (BPS-Bandpass Sampling) est appliquée et permet d’exploiter et certain nombre d’avantages liées au traitement du signal à Temps Discret (DT-Discrete Time signal processing), notamment le filtrage et la décimation. Si comparées à la Radio Logicielle, ces techniques permettent de relâcher les contraintes liées aux ADCs en maintenant des caractéristiques multistandard et de reconfigurabilité. Un simulateur dans le domaine fréquentiel large bande a été développé sous MATLAB pour répondre à des limitations au niveau système comme par exemple le repliement spectral et le produit gain bande. En addition avec une nouvelle méthode de conception système, cet outil permet de séparer les différentes contraintes des blocs pour la définition d’un plan de fréquence et the filtrage optimaux. La séparation des différentes contributions dans la dégradation du SNDR (notamment le bruit thermique, bruit de phase, non linéarité et le repliement), permet de relâcher de spécifications critiques liées à la consommation de puissance. L’architecture à sous échantillonnage proposée dans la thèse est résultat d’une comparaison quantitative des différentes architectures à sous échantillonnage, tout en appliquant la méthode et l’outil de conception système développés. Des aspects comme l’optimisation du filtrage entre les techniques à temps continu et temps discret et le plan de fréquence associé, permettent de trouve l’architecture qui représente le meilleur compromis entre la consommation électrique et l’agilité, dans le contexte voulu. Le bloc de filtrage à temps discret est identifié comme étant critique, et une étude sur les limitations d’implémentation circuit est menée. Des effets come les capacités parasites, l’imparité entre les capacités, le bruit du commutateur, la non linéarité, le gain finit de Ampli OP, sont évalués à travers d’une simulation comportementale en VHDL-AMS. On observe la robustesse des circuits orientés temps discret par rapport les contraintes des nouvelles technologies intégrés. Finalement, le système est spécifié en termes de bruit de phase, qui peuvent représenter jusqu’à 30% de la consommation en puissance. Dans ce but, une nouvelle méthode numérique est proposée pour être capable d’évaluer le rapport signal sur distorsion due au jitter SDjR dans le processus de sous échantillonnage. En plus, une conclusion non intuitive est survenue de cette étude, où on que réduire la fréquence d’échantillonnage n’augmente pas les contraintes en termes de jitter pour le système. L’architecture proposée issue de cette étude est sujet d’un développement circuit pour la validation du concept. / New needs on wireless communications pushes the development in terms reconfigurable, multistandards and low power radio systems. The objective of this work is to propose and design new receiver architecture capable of addressing these aspects in the context of the WPAN networks. The technique of Bandpass Sampling (BPS) is applied and permits to exploit a certain number of advantages linked to the discrete time (DT) signal processing, notably filtering and decimation. Compared to the Software-defined Radio (SDR), these techniques permit to relax the ADC constraints while keeping the multi standard and reconfigurable features. A wide band system level simulation tool is developed using MATLAB platform to overcome system level limitations such spectral aliasing and gain bandwidth product. In addition to a new system design method, the tool helps separating the blocks constraints and defining the optimum frequency plan and filtering. Separating the different contributions on the SNDR degradation (noise, phase noise, non linearity, and aliasing), critical specifications for power consumption can be relaxed. The proposed BPS architecture on the thesis is a result of a quantitative comparison of different BPS architectures, applying the system design method and tool. Aspects such filtering optimization between continuous and discrete time filtering and the associated frequency plan permitted to find the architecture which represents the best trade-off between power consumption and agility on the aimed context. The DT filtering block is therefore identified as critical block, which a study on the circuit implementation limitations is carried out. Effects such parasitic capacitances and capacitance mismatch, switch noise, non linear distortion, finite gain OTA, are evaluated through VHDL-AMS modelling. It is observed the robustness of discrete time oriented circuits. Finally, phase noise specifications are given considering that frequency synthesis circuits may represent up to 30% of the power consumption. For that goal, a new numerical method is proposed, capable of evaluating the signal to jitter distortion ratio SDjR on the BPS process. Moreover, a non intuitive conclusion is given, where reducing the sampling frequency does not increase the constraints in terms of jitter. The proposed architecture issue from this study is in stage of circuit level design in the project team of LETI for final proof of concept.

Ce manuscrit présente une méthode de conception au niveau système reposant sur la programmation fonctionnelle typée et visant à atténuer certains des problèmes complexifiant le développement des systèmes numériques modernes, tels que leurs tailles importantes ou la grande variété des blocs les constituant. Nous proposons un ensemble de mécanismes permettant de mélanger au sein d'un même design plusieurs formalismes de description distincts («modèles de calcul») se situant potentiellement à des niveaux d'abstraction différents. De plus, nous offrons au concepteur la possibilité d'expliciter directement les paramètres explorables de chaque sous-partie du design, puis d'en déterminer des valeurs acceptables via une étape d'exploration partiellement ou totalement automatisée réalisée à l'échelle du système. Les gains qu'apportent ces stratégies nouvelles sont illustrés sur plusieurs exemples. / This work presents a novel system-level design method based on typed functional programming and aiming at mitigating some of the issues making the development of modern digital systems complex, such as their increasing sizes and the variety of their subcomponents. We propose a range of mechanisms allowing to mix within a single design several description formalisms (``models of computation''), possibly at different abstraction levels. Moreover, the designer is provided with means to directly express the explorable parameters of each part of their design, and to find acceptable values for them through a partially or totally automatic system-wide architectural exploration step. The advantages brought by those new strategies are illustrated on several examples.

L’objectif des travaux menés dans le cadre de cette thèse est le déploiement d’un dispositif médical embarqué et portable assurant l’acquisition et la transmission du signal biomédical électrocardiogramme. Il doit intégrer des techniques de traitement avancées et un étage de communication radio. A la quête de nouvelles idées non encore explorées par la communauté scientifique, nous proposons dans notre travail d’appliquer une acquisition compressée intelligente par exploitation du caractère parcimonieux du signal électrocardiogramme à l’aide d’un convertisseur analogique-numérique à échantillonnage non-uniforme. / The objective of this thesis is the deployment of an embedded and portable medical device for acquisition and transmission of the biomedical electrocardiogram signal. The device incorporates advanced processing techniques and a radio communication module. In search of new ideas not yet explored by the scientific community, we propose in our work to apply an intelligent compressed acquisition by exploiting the sparsity character of the electrocardiogram using a non-uniform sampling analog-to-digital converter.