Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications. However, planar integration technology is a packaging approach with a large contact area between different materials. This may result in unknown failure mechanisms in power applications. Extensive research has already been done to study the performance, processing, and reliability of the planar interconnects in thin film structures. The thickness of the thin films used in integrated circuits (IC) or microelectronics applications ranges from the magnitude of nanometers to that of micrometers. In this work, we are interested in adopting planar interconnections to Integrated Power Electronics Modules (IPEM). In Integrated Power Electronics Modules (IPEMs), copper traces, especially bus traces, need to conduct current ranging from a few amps to tens of amps. One of the major differences between IC and IPEM is that the metal layer in IPEMs (normally >75µm) is much thicker than that of the thin films in IC (normally <1µm). The other major difference, which is also a feature of IPEM, is that the planar metallization is deposited on different brittle substrates. In active IPEM, switching devices are in a bare die form with no encapsulation. The copper deposition is on top of the silicon chips and the insulation polyimide layer. One of the key elements for passive IPEM and the EMI IPEM is the integrated inductor-capacitor (LC) module, which realizes equivalent inductors and capacitors in one single module. The deposition processes for silicon substrates and ceramic substrates are compatible and both the silicon and ceramic materials are brittle. Under high current and high temperature conditions, these copper depositions on brittle materials will cause detrimental failure spots. Over the last few years, the design, manufacture, optimization, and testing of the IPEMs has been developed and well documented. Up to this time , the research on failure mechanisms of conventional integrated power modules has led to the understanding of failures centered on wire bond or solder layer. However, investigation on the reliability and failure modes of IPEM is lacking, particularly that which uses metallization on brittle substrates for high current operations. In this study, we conduct experiments to measure and calculate the residual stresses induced during the process. We also, theoretically model and simulate the thermo-mechanical stresses caused by the mismatch of thermal expansion coefficients between different materials in the integrated power modules. In order to verify the simulation results, the integrated power modules are manufactured and subjected to the lifetime tests, in which both power cycling and temperature cycling tests are carried out. The failure mode analysis indicates that there are different failure modes for copper films under tensile or compressive stresses. The failure detection process verifies that delamination and silicon cracks happen to copper films due to compressive and tensile stresses respectively. This study confirms that the high stresses between the metallization and the silicon are the failure drivers in integrated power electronics modules.. We also discuss the driving forces behind several different failure modes. Further understanding of thesefailure mechanisms enables the failure modes to be engineered for safer electrical operation of IPEM modules and helps to enhance the reliability of system-level operation. It is also the basis to improve the design and to optimize the process parameters so that IPEM modules can have a high resistance to recognized failures. / Ph. D.

<p>Bonding techniques intended for assembling space microsystems are studied in this work. One of the largest problems in bonding pre-processed semiconductor wafers are the severe process restrictions imposed by material compatibility issues. Plasma processes have shown to be good for sensitive materials integration why the influence of different plasma parameters on the bondability of wafers is particularly studied. Conventional wet chemical and field-assisted methods are also examined. The resulting bond quality is assessed in terms of mechanical strength, homogeneity, and yield.</p><p>The effect of spaceflight environment on the reliability of wafer bonds is also investigated. Both high and low temperature annealed bonds are found to be very robust. Effects observed are that low temperature bonds are reinforced by thermal cycling in vacuum and that high temperature bonds degrade slightly by low dose γ irradiation.</p><p>Adhesion quantification is important for all bonding. Development of accurate quantification methods is considered necessary since most methods at hand are limited. This work includes the development of the blister test method. Former test structures are improved to be more practical to work with and to yield low experimental scatter. A physical stress model for the improved structure is suggested with which successful predictions of fracture for different test specimen configurations are made. The blister test method is used throughout this work to assess the strength of wafer bonds. The physics background and modelling of other common test methods are also thoroughly analysed. The methods’ practical capabilities and limitations are commented; origin and mitigation of measurement errors are discussed. It is shown that all methods can be significantly improved by small means.</p><p>Weibull statistics is introduced as a tool to characterise wafer bonds. This method is suitable to use in brittle materials design as the inherent variability in strength can be properly accounted for.</p>

Bonding techniques intended for assembling space microsystems are studied in this work. One of the largest problems in bonding pre-processed semiconductor wafers are the severe process restrictions imposed by material compatibility issues. Plasma processes have shown to be good for sensitive materials integration why the influence of different plasma parameters on the bondability of wafers is particularly studied. Conventional wet chemical and field-assisted methods are also examined. The resulting bond quality is assessed in terms of mechanical strength, homogeneity, and yield. The effect of spaceflight environment on the reliability of wafer bonds is also investigated. Both high and low temperature annealed bonds are found to be very robust. Effects observed are that low temperature bonds are reinforced by thermal cycling in vacuum and that high temperature bonds degrade slightly by low dose γ irradiation. Adhesion quantification is important for all bonding. Development of accurate quantification methods is considered necessary since most methods at hand are limited. This work includes the development of the blister test method. Former test structures are improved to be more practical to work with and to yield low experimental scatter. A physical stress model for the improved structure is suggested with which successful predictions of fracture for different test specimen configurations are made. The blister test method is used throughout this work to assess the strength of wafer bonds. The physics background and modelling of other common test methods are also thoroughly analysed. The methods’ practical capabilities and limitations are commented; origin and mitigation of measurement errors are discussed. It is shown that all methods can be significantly improved by small means. Weibull statistics is introduced as a tool to characterise wafer bonds. This method is suitable to use in brittle materials design as the inherent variability in strength can be properly accounted for.

Thin layers are widely used in many fields of technology and today we can say that they are found in all modern technologies. Thin layers can be created in two ways, namely by chemical or physical means. This work focuses on the latter method, more particularly a technology of thermal evaporation of thin layers in a vacuum. The work focuses on the process principles during and after the evaporation. Much of the work focuses on the development and design of experiments. These experiments illustrate some of the phenomena that take place on thin films produced by the aforementioned technology. Work helps to better understand processes during formation of thin layers and properties that influence the quality and stability of thin films. In conclusion we describe results of experiments and new developments in the field of thin films deposition using evaporation under vakuum are summarized.

De nos jours, la durée de vie des modules d’électronique de puissance est désormais limitée par les technologies standards de conditionnement, telles que le câblage par fils et le brasage. Ainsi une optimisation des technologies actuellement employées n’est pas suffisante pour satisfaire les futures exigences de fiabilité. Pour dépasser ces limites, un nouveau module de puissance remplaçant les fils de connexion par des clips en cuivre a été développé. Ce design innovant vise à améliorer la fiabilité du module puisqu’il empêche la dégradation des fils de connexion, constituant bien souvent la principale source de défaillance. La contrepartie de ce gain de fiabilité réside dans la complexification de la structure interne du module. En effet, l’emploi d’un clip en cuivre nécessite une brasure supplémentaire fixant le clip à la puce. Ainsi, le comportement thermomécanique et les différents modes de rupture auxquels le composant est soumis lors de son utilisation doivent être caractérisés. Cette étude utilise la simulation numérique pour analyser avec précision le comportement de chaque couche de matériaux lors des cycles actifs de puissance. De plus, une étude de sensibilité à la fois expérimentale et numérique concernant les paramètres de tests est réalisée. Les zones critiques du module ainsi que les combinaisons critiques des paramètres de tests pour les différents modes de rupture sont mis en évidence. Par ailleurs, une analyse en mécanique de la rupture est conduite et la propagation des fissures à différentes zones clés est analysée en fonction des différents paramètres de tests. Les résultats obtenus permettent la définition de modèles de prédiction de durée de vie. / Today a point has been reached where safe operation areas and lifetimes of power modules are limited by the standard packaging technologies, such as wire bonding and soft soldering. As a result, further optimization of used technologies will no longer be sufficient to meet future reliability requirements. To surpass these limits, a new power module was designed using Cu clips as interconnects instead of Al wire bonds. This new design should improve the reliability of the module as it avoids wire bond fatigue failures, often the root cause of device failures. The counterpart for an improved reliability is a quite complicated internal structure. Indeed, the use of a Cu clip implies an additional solder layer in order to fix the clip to the die. The thermo-mechanical behavior and failure mechanisms of such a package under application have to be characterized. The present study takes advantage of numerical simulations to precisely analyze the behavior of each material layer under power cycling. Furthermore an experimental and numerical sensitivity study on tests parameters is conducted. Critical regions of the module are pointed out and critical combinations of tests parameters for different failure mechanisms are highlighted. Then a fracture mechanics analysis is performed and the crack growth at different locations is analyzed in function of different tests parameters. Results obtained enable the definition of lifetime prediction models.