In modern microprocessors, thermal management has become one of the main hurdles in continued performance enhancement. Cooling schemes utilizing single phase microfluidics have been investigated extensively for enhanced heat dissipation from microprocessors. However, two-phase fluidic cooling devices are becoming a promising approach, and are less understood. This study aims to examine two-phase flow and heat transfer within a pin-fin enhanced micro-gap. The pin-fin array covered an area of 1cm x 1cm and had a pin diameter, height and pitch of 150μm, 200μm and 225μm, respectively, (aspect ratio of 1.33). This study covers both uniformly and partially heated scenarios. The working fluid used was R245fa. The average heat transfer coefficient and high speed flow visualization results indicated a rapid transition to the annular flow regime with a strong dependence on heat flux. Also, unique, conically-shaped two-phase wakes were observed, demonstrating the lateral spreading capability of the pin-fin array geometry.

The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.

With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.

This research reports for the first time conductive anodic filament reliability of copper plated-through-vias with spacing of 75 – 200 µm in thin glass fiber reinforced organic packaging substrates with advanced epoxy-based and cyclo-olefin polymer resin systems. Reliability studies were conducted in halogenated and halogen-free substrates with improved test structure designs including different conductor spacing and geometry. Accelerated test condition (temperature, humidity and DC bias voltage) was used to investigate the effect of conductor spacing and substrate material influence on insulation reliability behavior. Characterization studies included gravimetric measurement of moisture sorption, extractable ion content analysis, electrical resistance measurement, impedance spectroscopy measurement, optical microscopy and scanning electron microscopy analysis and elemental characterization using energy dispersive x-ray spectroscopy. The accelerated test results and characterization studies indicated a strong dependence of insulation failures on substrate material system, conductor spacing and geometry. This study presents advancements in the understanding of failure processes and chemical nature of failures in fine-pitch copper plated-through-vias in newly developed organic substrates and demonstrates potential methods to mitigate failures for high density organic packages.

The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.

In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems. This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.