Panoramic virtual reality is an emerging technology that has recently gained the attention of both the research community and regular consumers. It allows the users to immerse themselves in omnidirectional videos with the help of a virtual reality headset : thanks to an increasing amount of affordable head-mounted-displays, any recent smartphone can offer a decent panoramic virtual reality experience. However since omnidirectional videos are videos with a large field-of-view that covers the entire sphere around the camera, they require large resolutions and thus high bitrates. This master degree project conducted at RE’FLEKT GmbH is an exploratory work that seeks to reduce the panoramic video bitrate. Because of the nature of omnidirectional videos, the user can only see a subpart of each video frame, and thus some zones of the video can attract more attention than others. The purpose of this study is to introduce the concept of region-of-interest encoding in panoramic VR. The main contribution is a method to encode panoramic videos in an H.264 video format stream with a space-variant level of details depending on the zones that attract the most the viewers’ interest. First, the region-of-interest are detected through a head-tracking module combined with a Gaussian attention model. Then, the reference video is encoded with the open source x264 encoder, with a quantization step adjusted to the region-of-interest information. The International Telecommunications Union standard subjective tests show that this method can perform better than classic H.264 encoding only in specific cases. / Panoramisk virtuell verklighet (VR) är en kommande teknik som nyligen har mött intresse från forskarsamhället och vanliga konsumenter. Det gör det möjligt för användarna att fördjupa sig i videor upptagna från flera riktningar, med hjälp av ett VR-headset : tack vare ett växande antal billiga och huvudburna bildskärmar, erbjuder alla nya smarttelefoner en passande panoramisk VR-erfarenhet. Men på grund av den breda synvinkeln i flerriktade media behöver videor med 360 graders synfält stor upplösning och därför höga bithastigheter. Detta masterexamensarbete som utförts på RE’FLEKT GmbH är ett utforskande arbete som strävar efter att reducera panoramabildens bithastighet. I flerriktade videoklipp kan användaren bara se en del av varje bildruta, härigenom får somliga zoner mer uppmärksamhet än andra. Syftet med denna studie är att introducera begreppet region-av-intresse (ROI) kodning i panoramisk VR. Huvudbidraget är en metod för att koda panoramisk video i en H.264-ström med en varierande nivå av detaljer som beror på de zoner som får mest av tittarnas intresse. Först detekteras ROI genom en huvudspårningsmodul kombinerad med en gaussisk uppmärksamhetsmodell. Därefter kodas referensvideoen med x264-kodaren (öppen källkod) med hjälp av ROI-informationen. ITU-standardens subjektiva test visar att den här metoden kan fungera bättre än klassisk H.264-kodning i enskilda fall.

Esta dissertação de mestrado apresenta um novo esquema de controle de taxa hierárquico – HRC – para o padrão MVC – extensão para vídeos de múltiplas vistas do padrão H.264 – com objetivo de melhorar o aproveitamento da largura de banda oferecida por um canal entregando o vídeo comprimido com a melhor qualidade possível. Este esquema de controle de taxa hierárquico foi concebido para controlar de forma conjunta os níveis de quadro e de unidades básicas (BU). O esquema proposto explora a correlação existente entre as distribuições das taxas de bits em quadros vizinhos para predizer de forma eficiente o comportamento dos futuras bitrates através da aplicação de um controle preditivo baseado em modelos – MPC – que define uma ação de controle apropriada sobre as ações de adaptação do parâmetro de quantização (QP). Para prover um ajuste em granularidade fina, o QP é adicionalmente adaptado internamente para cada quadro por um processo de decisão de Markov (MDP) implementado em nível de BU capaz de considerar mapas com Regiões de Interesse (RoI). Um retorno acoplado aos dois níveis supracitados é realizado para garantir a consistência do sistema. Aprendizagem por Reforço é utilizada para atualizar os parâmetros do Controle Preditivo baseado em Modelos e do processo de decisão de Markov. Resultados experimentais mostram a superioridade da utilização do esquema de controle proposto, comparado às soluções estado-da-arte, tanto em termos de precisão na alocação de bits quanto na otimização da razão taxa-distorção, entregando um vídeo de maior qualidade visual nos níveis de quadros e de BUs. / This master thesis presents a novel Hierarchical Rate Control – HRC – for the Multiview Video Coding standard targeting an increased bandwidth usage and high video quality. The HRC is designed to jointly address the rate control at both framelevel and Basic Unit (BU)-level. This scheme is able to exploit the bitrate distribution correlation with neighboring frames to efficiently predict the future bitrate behavior by employing a Model Predictive Control that defines a proper control action through QP (Quantization Parameter) adaptation. To provide a fine-grained tuning, the QP is further adapted within each frame by a Markov Decision Process implemented at BU-level able to take into consideration a map of the Regions of Interest. A coupled frame/BU-level feedback is performed in order to guarantee the system consistency. A Reinforcement Learning method is responsible for updating the Model Predictive Control and the Markov Decision Process parameters. Experimental results show the superiority of the Hierarchical Rate Control compared to state-of-the-art solutions, in terms of bitrate allocation accuracy and rate-distortion, while delivering smooth video quality at both frame and Basic Unit levels.

Esta dissertação de mestrado apresenta um novo esquema de controle de taxa hierárquico – HRC – para o padrão MVC – extensão para vídeos de múltiplas vistas do padrão H.264 – com objetivo de melhorar o aproveitamento da largura de banda oferecida por um canal entregando o vídeo comprimido com a melhor qualidade possível. Este esquema de controle de taxa hierárquico foi concebido para controlar de forma conjunta os níveis de quadro e de unidades básicas (BU). O esquema proposto explora a correlação existente entre as distribuições das taxas de bits em quadros vizinhos para predizer de forma eficiente o comportamento dos futuras bitrates através da aplicação de um controle preditivo baseado em modelos – MPC – que define uma ação de controle apropriada sobre as ações de adaptação do parâmetro de quantização (QP). Para prover um ajuste em granularidade fina, o QP é adicionalmente adaptado internamente para cada quadro por um processo de decisão de Markov (MDP) implementado em nível de BU capaz de considerar mapas com Regiões de Interesse (RoI). Um retorno acoplado aos dois níveis supracitados é realizado para garantir a consistência do sistema. Aprendizagem por Reforço é utilizada para atualizar os parâmetros do Controle Preditivo baseado em Modelos e do processo de decisão de Markov. Resultados experimentais mostram a superioridade da utilização do esquema de controle proposto, comparado às soluções estado-da-arte, tanto em termos de precisão na alocação de bits quanto na otimização da razão taxa-distorção, entregando um vídeo de maior qualidade visual nos níveis de quadros e de BUs. / This master thesis presents a novel Hierarchical Rate Control – HRC – for the Multiview Video Coding standard targeting an increased bandwidth usage and high video quality. The HRC is designed to jointly address the rate control at both framelevel and Basic Unit (BU)-level. This scheme is able to exploit the bitrate distribution correlation with neighboring frames to efficiently predict the future bitrate behavior by employing a Model Predictive Control that defines a proper control action through QP (Quantization Parameter) adaptation. To provide a fine-grained tuning, the QP is further adapted within each frame by a Markov Decision Process implemented at BU-level able to take into consideration a map of the Regions of Interest. A coupled frame/BU-level feedback is performed in order to guarantee the system consistency. A Reinforcement Learning method is responsible for updating the Model Predictive Control and the Markov Decision Process parameters. Experimental results show the superiority of the Hierarchical Rate Control compared to state-of-the-art solutions, in terms of bitrate allocation accuracy and rate-distortion, while delivering smooth video quality at both frame and Basic Unit levels.

Esta dissertação de mestrado apresenta um novo esquema de controle de taxa hierárquico – HRC – para o padrão MVC – extensão para vídeos de múltiplas vistas do padrão H.264 – com objetivo de melhorar o aproveitamento da largura de banda oferecida por um canal entregando o vídeo comprimido com a melhor qualidade possível. Este esquema de controle de taxa hierárquico foi concebido para controlar de forma conjunta os níveis de quadro e de unidades básicas (BU). O esquema proposto explora a correlação existente entre as distribuições das taxas de bits em quadros vizinhos para predizer de forma eficiente o comportamento dos futuras bitrates através da aplicação de um controle preditivo baseado em modelos – MPC – que define uma ação de controle apropriada sobre as ações de adaptação do parâmetro de quantização (QP). Para prover um ajuste em granularidade fina, o QP é adicionalmente adaptado internamente para cada quadro por um processo de decisão de Markov (MDP) implementado em nível de BU capaz de considerar mapas com Regiões de Interesse (RoI). Um retorno acoplado aos dois níveis supracitados é realizado para garantir a consistência do sistema. Aprendizagem por Reforço é utilizada para atualizar os parâmetros do Controle Preditivo baseado em Modelos e do processo de decisão de Markov. Resultados experimentais mostram a superioridade da utilização do esquema de controle proposto, comparado às soluções estado-da-arte, tanto em termos de precisão na alocação de bits quanto na otimização da razão taxa-distorção, entregando um vídeo de maior qualidade visual nos níveis de quadros e de BUs. / This master thesis presents a novel Hierarchical Rate Control – HRC – for the Multiview Video Coding standard targeting an increased bandwidth usage and high video quality. The HRC is designed to jointly address the rate control at both framelevel and Basic Unit (BU)-level. This scheme is able to exploit the bitrate distribution correlation with neighboring frames to efficiently predict the future bitrate behavior by employing a Model Predictive Control that defines a proper control action through QP (Quantization Parameter) adaptation. To provide a fine-grained tuning, the QP is further adapted within each frame by a Markov Decision Process implemented at BU-level able to take into consideration a map of the Regions of Interest. A coupled frame/BU-level feedback is performed in order to guarantee the system consistency. A Reinforcement Learning method is responsible for updating the Model Predictive Control and the Markov Decision Process parameters. Experimental results show the superiority of the Hierarchical Rate Control compared to state-of-the-art solutions, in terms of bitrate allocation accuracy and rate-distortion, while delivering smooth video quality at both frame and Basic Unit levels.

This thesis looks at hardware algorithms that help reduce dynamic power dissipation in video encoder applications. Computational complexity of motion estimation and the data traffic between external memory and the video processing engine are two main reasons for large power dissipation in video encoders. While motion estimation may consume 50% to 70% of total video encoder power, the power dissipated in external memory such as the DDR SDRAM can be of the order of 40% of the total system power. Reducing power dissipation in video encoders is important in order to improve battery life of mobile devices such as the smart phones and digital camcorders. We propose hardware algorithms which extract only the important features in the video data to reduce the complexity of computations, communications and storage, thereby reducing average power dissipation. We apply this concept to design hardware algorithms for optimizing motion estimation matching complexity, and reference frame storage and access from the external memory. In addition, we also develop techniques to reduce searching complexity of motion estimation. First, we explore a set of adaptive algorithms that reduce average power dissipated due to motion estimation. We propose that by taking into account the macro-block level features in the video data, the average matching complexity of motion estimation in terms of number of computations in real-time hardwired video encoders can be significantly reduced when compared against traditional hardwired implementations, that are designed to handle most demanding data sets. Current macro-block features such as pixel variance and Hadamard transform coefficients are analyzed, and are used to adapt the matching complexity. The macro-block is partitioned based on these features to obtain sub-block sums, which are used for matching operations. Thus, simple macro-blocks, without many features can be matched with much less computations compared to the macro-blocks with complex features, leading to reduction in average power dissipation. Apart from optimizing the matching operation, optimizing the search operation is a powerful way to reduce motion estimation complexity. We propose novel search optimization techniques including (1) a center-biased search order and (2) skipping unlikely search positions, both applied in the context of real time hardware implementation. The proposed search optimization techniques take into account and are compatible with the reference data access pattern from the memory as required by the hardware algorithm. We demonstrate that the matching and searching optimization techniques together achieve nearly 65% reduction in power dissipation due to motion estimation, without any significant degradation in motion estimation quality. A key to low power dissipation in video encoders is minimizing the data traffic between the external memory devices such as DDR SDRAM and the video processor. External memory power can be as high as 50% of the total power budget in a multimedia system. Other than the power dissipation in external memory, the amount of data traffic is an important parameter that has significant impact on the system cost. Large memory traffic necessitates high speed external memories, high speed on-chip interconnect, and more parallel I/Os to increase the memory throughput. This leads to higher system cost. We explore a lossy, scalar quantization based reference frame compression technique that can be used to reduce the amount of reference data traffic from external memory devices significantly. In this scheme, the quantization is adapted based on the pixel range within each block being compressed. We show that the error introduced by the scalar quantization is bounded and can be represented by smaller number of bits compared to the original pixel. The proposed reference frame compression scheme uses this property to minimize the motion compensation related traffic, thereby improving the compression scheme efficiency. The scheme maintains a fixed compression ratio, and the size of the quantization error is also kept constant. This enables easy storage and retrieval of reference data. The impact of using lossy reference on the motion estimation quality is negligible. As a result of reduction in DDR traffic, the DDR power is reduced significantly. The power dissipation due to additional hardware required for reference frame compression is very small compared to the reduction in DDR power. 24% reduction in peak DDR bandwidth and 23% net reduction in average DDR power is achieved. For video sequences with larger motion, the amount of bandwidth reduction is even higher (close to 40%) and reduction in power is close to 30%.

Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconfigurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications. The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding. We present an unified software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconfigurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve flexible communication across different tiles. Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataflow models of computation. The implementation model leads to a process network oriented compilation flow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full hardware configurations of a video decoder. The thesis also presents an application QoS aware scheduler that selects a decoder configuration that best meets the application performance requirements, thereby enabling dynamic performance scaling. The memory hierarchy of Polymorphic ASIC makes use of an application specific cache. Through a combined analysis of miss rate and external memory bandwidth, we show that the degradation in decoder performance due to memory stall cycles depends on the properties of the video being decoded as well as the behavior of the external memory interface. Based on this observation, we present the design of a reconfigurable 2–D cache architecture which can adjust its parameters in accordance with the characteristics of the video stream being decoded. We validate the Polymorphic ASIC using a proof–of–concept implementation on an FPGA. The performance of H.264 decoder on Polymorphic ASIC is evaluated for uniprocessor, multi processor, hardware accelerated and full hardware configurations. The scaling in performance delivered by these configurations shows that the Polymorphic ASIC enables the application to achieve super linear speedups [1]. The experimental results show that different implementations of a H.264 video decoder on the Polymorphic ASIC can deliver performance comparable to a wide spectrum of devices ranging from embedded processor like ARM 9 to MPSoCs like IBM Cell. We also present the energy consumption of various configurations of video decoders on Polymorphic ASIC and an application to configuration mapping aimed at minimizing the overall energy consumption of a Polymorphic ASIC.

Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconfigurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications. The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding. We present an unified software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconfigurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve flexible communication across different tiles. Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataflow models of computation. The implementation model leads to a process network oriented compilation flow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full hardware configurations of a video decoder. The thesis also presents an application QoS aware scheduler that selects a decoder configuration that best meets the application performance requirements, thereby enabling dynamic performance scaling. The memory hierarchy of Polymorphic ASIC makes use of an application specific cache. Through a combined analysis of miss rate and external memory bandwidth, we show that the degradation in decoder performance due to memory stall cycles depends on the properties of the video being decoded as well as the behavior of the external memory interface. Based on this observation, we present the design of a reconfigurable 2–D cache architecture which can adjust its parameters in accordance with the characteristics of the video stream being decoded. We validate the Polymorphic ASIC using a proof–of–concept implementation on an FPGA. The performance of H.264 decoder on Polymorphic ASIC is evaluated for uniprocessor, multi processor, hardware accelerated and full hardware configurations. The scaling in performance delivered by these configurations shows that the Polymorphic ASIC enables the application to achieve super linear speedups [1]. The experimental results show that different implementations of a H.264 video decoder on the Polymorphic ASIC can deliver performance comparable to a wide spectrum of devices ranging from embedded processor like ARM 9 to MPSoCs like IBM Cell. We also present the energy consumption of various configurations of video decoders on Polymorphic ASIC and an application to configuration mapping aimed at minimizing the overall energy consumption of a Polymorphic ASIC.

The video on demand streaming is raising drastically in popularity, bringing new challenges to the video coding field. There is a need for new video coding techniques that improve performance and reduce the bitrates. One of the most promising areas of research is perceptual video coding where attributes of the human visual system are considered to minimize visual redundancy. The visual attention only makes it possible for humans to focus on a smaller region at the time, which is led by different cues, and with deep neural networks it has become possible to create high-accuracy models of this. The purpose of this study is therefore to investigate how adaptive quantization (AQ) based on a deep visual attention model can be used to improve the subjective video quality for low bitrates. A deep visual attention model was integrated into the encoder x265 to control how the bits are distributed on frame level by adaptively setting the quantization parameter. The effect on the subjective video quality was evaluated through A/B testing where the solution was compared to one of the standard methods for AQ in x265. The results show that the ROI-based AQ was perceived to be of better quality in one out of ten cases. The results can partly be explained by certain methodological choices, but also highlights a need for more research on how to make use of visual attention modeling in more complex real-world streaming scenarios to make streaming content more accessible and reduce bitrates. / "Video on demand"-streamingen ökar kraftigt i popularitet vilket skapar nya utmaningar inom video kodning. Det finns ett behov av nya videokodningstekniker som ökar prestanda och reducerar bithastigheten. Ett av de mest lovade forskningsområdena är perceptuell videokodning där man tar hänsyn till synens egenskaper för att minimera visuell redundans. Det visuella fokuset gör att människan bara kan fokusera på ett mindre områden åt gången, lett av olika typer av signaler, och med hjälp av djupa neurala nätverk har det blivit möjligt att skapa välpresterande modeller av det. Syftet med denna studie är därför att undersöka hur adaptiv kvantisering baserat på en djupinlärningsmodell av visuellt fokus kan användas för att förbättra den subjektiva videokvaliteten för låga bithastigheter. En djup modell av visuellt fokus var integrerad i videokodaren x265 för att kontrollera hur bitarna ditribueras på bildnivå genom att adaptivt sätta kvantiseringsparametern. Den subjektiva videokvaliteten utvärderades genom A/B tester där lösningen jämfördes med en standardmetod för adaptiv kvantisering i x265. Resultaten visar att den visuellt fokus-baserade adaptiva kvantiseringen upplevdes ge bättre kvalitet i ett av tio fall. Detta resultat kan delvis förklaras av vissa metodval, men visar också på ett behov för mer forskning på hur modeller för visuellt fokus kan användas i mer komplexa och verkliga streamingscenarion för att kunna göra innehållet mer tillgängligt och reducera bithastigheten.

The high demand of the video decoding has pushed the developers to implement the decoders on parallel architectures. This thesis provides the deliberations about the implementation of an MPEG-4 decoder on a massively parallel processor array (MPPA), Ambric 2045, by converting the CAL actor language implementation of the decoder. This decoder is the Xilinx model of the MPEG-4 Simple Profile decoder and consists of four main blocks; parser, acdc, idct2d and motion. The parser block is developed in another thesis work [20] and the rest of the decoder, which consists of the other three blocks, is implemented in this thesis work. Afterwards, in order to complete the decoder, the parser block is combined with the other three blocks. Several methods are developed for conversion purposes. Additionally, a number of other methods are developed in order to overcome the constraints of the ambric architecture such as no division support. At the beginning, for debugging purposes, the decoder is implemented on a simulator which is designed for Ambric architecture. Finally the implementation is uploaded to the Ambric 2045 chip and tested with different input streams. The performance of the implementation is analyzed and satisfying results are achieved when compared to the standards which are in use in the market. These performance results can be considered as satisfying for any real-time application as well. Furthermore, the results are compared with the results of the CAL implementation, running on a single 2GHz i7 intel processor, in terms of speed and efficiency. The Ambric implementation runs 4,7 times faster than the CAL implementation when a small input stream (300 frames with resolution of 176x144) is used. However, when a large input stream (384 frames with resolution of 720x480) is used, the Ambric implementation shows a performance which is approximately 32 times better than the CAL implementation, in terms of decoding speed and throughput. The performance may increase further together with the size of the input stream up to some point.

Immersion based technologies such as Augmented Reality (AR), Virtual Reality (VR) and Mixed Reality (MR), together falling under the umbrella of Extended Reality (XR) have taken the world by storm in the recent past. However, with the growing market and the increasing number of applications of XR, multiple challenges have arisen. To maintain acceptable levels of motion-to-photon latency, there is a need to serve the users with ultra low latency and with high reliability. To provide high quality rendering, these solutions have traditionally been deployed with wired connections, but severely inhibiting user mobility. Thus, the need to develop wireless solutions promising ultra low latency and high reliability emerges. Cloud/Edge based solutions promise to provide great dividends in this regard but it still remains crucial to understand how different scheduling policies perform against one another in terms of average throughput, mean system time, the number of UEs which can be serviced simultaneously etc. In this thesis, we explore how online packet scheduling policies such as first-come-first-serve, earliestdeadline-first, maximum weight scheduling etc. compare against other Quality of Experience(QoE)/ packet weight aware online scheduling policies and also against optimal offline schemes such as maximum-weighted-bipartitematching. We perform a detailed analysis of how these policies fare by studying various metrics such as the average-packet system time, competitive ratios, packet drop percentages and weight throughput, amongst others. Finally, we also explore how the introduction of multi-layered video encoding impacts XR service. Amongst the findings of the thesis, we conclude that it is possible to come up with solutions such as EDFα (which is a deadline and weight aware derivative of the earliest deadline first scheduling policy), which can either increase the weight throughput when compared to other baselines while also providing lesser packet drops and lower average system times for the scheduled packets. This algorithm can be further tuned by varying α to accordingly alter the weight throughput, system time and packet drop ratio depending on the precise user application. Additionally, we establish with the help of simulations that the introduction of multi-layered video encoding conclusively helps in reducing the average system time and eventually allows for more users to be accommodated in an XR based system at the cost of worsening video quality. / Immersionsbaserade teknologier som Augmented Reality (AR), Virtual Reality (VR) och Mixed Reality (MR), som tillsammans faller under paraplyet Extended Reality (XR) har tagit världen med storm på senare tid. Men med den växande marknaden och det ökande antalet tillämpningar av XR har flera utmaningar uppstått. För att förhindra åksjuka hos användare och för att upprätthålla acceptabla nivåer av rörelse-till-foton-latens, finns det ett behov av att betjäna användarna med ultralåg latens och med hög tillförlitlighet. För att ge högkvalitativ rendering har dessa lösningar traditionellt implementerats med trådbundna anslutningar, men de hämmar kraftigt användarens rörlighet. Därför uppstår behovet av att utveckla trådlösa lösningar som lovar ultralåg latens och hög tillförlitlighet. Moln/Edge-baserade lösningar lovar att ge stor utdelning i detta avseende, men det är fortfarande viktigt att förstå hur olika schemaläggningspolicyer fungerar mot varandra när det gäller genomsnittlig genomströmning, genomsnittlig systemtid, antalet UE:er som kan betjänas samtidigt etc. I den här avhandlingen undersöker vi hur online-paketschemaläggningspolicyer som round robin, först till kvarnförst-kvarn, tidigast-deadline-först, schemaläggning för maximal vikt etc. jämförs med andra Quality of Experience (QoE)/Viktmedvetna onlineschemaläggningspolicyer och även mot optimala offline-scheman såsom maximalt viktad-bipartite-matchning. Vi utför en detaljerad analys av hur dessa policyer klarar sig genom att studera olika mätvärden, såsom den genomsnittliga paketets systemtid, konkurrensförhållanden, procentsatser för paketnedgång och viktad genomströmning, bland annat. Slutligen undersöker vi också hur introduktionen av flerskiktad videokodning påverkar XRtjänsten. Bland resultaten av avhandlingen drar vi slutsatsen att det är möjligt att komma med lösningar som EDFα (som är en deadline- och viktmedveten derivata av Earliest deadline first scheduling policy), som antingen kan öka den viktade genomströmning jämfört med andra baslinjer samtidigt som det ger mindre paketnedgångar och lägre genomsnittliga systemtider för de schemalagda paketen. Denna algoritm kan ställas in ytterligare genom att variera α för att följaktligen ändra den viktade genomströmningen, systemtiden och paketnedgångshastigheten beroende på den exakta användarapplikationen. Dessutom fastställer vi med hjälp av simuleringar att införandet av flerskiktsvideokodning definitivt hjälper till att minska den genomsnittliga systemtiden och så småningom tillåter fler användare att få plats i ett XR-baserat system.