The decline of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with the need for real-time data logging has created a growing demand for robust, high temperature RF electronics. This thesis presents the design of an intermediate frequency (IF) variable gain amplifier (VGA) for downhole communications, which can operate up to an ambient temperature of 230 °C. The proposed VGA is designed using 0.25 μm GaN on SiC high electron mobility transistor (HEMT) technology. Measured results at 230 °C show that the VGA has a peak gain of 27dB at center frequency of 97.5 MHz, and a gain control range of 29.4 dB. At maximum gain, the input P1dB is -11.57 dBm at 230 °C (-3.63 dBm at 25 °C). Input return loss is below 19 dB, and output return loss is below 12 dB across the entire gain control range from 25 °C to 230 °C. The variation with temperature (25 °C to 230 °C) is 1 dB for maximum gain, and 4.7 dB for gain control range. The total power dissipation is 176 mW for maximum gain at 230 °C. / Master of Science

ARE subfamily proteins belonging to ABC transporters confers a different degree of resistance to macrolides, linkosamides and streptogramins antibiotics. Among the most clinically ARE subfamily proteins in staphylococci is Vga(A) protein lead to the award resistance to streptogtramins A. In 2006, discovered the new variant called the Vga(A)LC, which in addition to streptogramins A resistance also confers linkosamides. Vga(A) and Vga(A)LC differ in only 7 amino acids, yet confer different resistance phenotypes. In previous experiments it was found that the central role in determining substrate specificity play a 4 amino acid differences that accumulate in the section of 15 amino acids within the linker connecting the two ABC domains (positions 212, 219, 220 and 226). The combination of amino acids LGAG Vga(A) increases resistance to streptogramins A while present in combination SVTS Vga(A)LC increased resistance to linkosamides. Although in this subfamily includes a large number of resistance proteins, the mechanism of resistance has not yet been established with certainty. The aim was to create a new Vga(A) variants that contain specific combinations of amino acids for Vga(A) and Vga(A)LC protein at positions 212, 219, 220 and 226 and compared their ability to grant resistance to linkosamides. We also...

<p>Denna rapport behandlar konstruktion och tillverkning av ett videokort till Versa Module Eurocard (VME) bussen. Kortet skall användas vid laborationer i kurser där mikrodatorkort VM42 från PEP Modular Computer används. Grafikkortet klarar en upplösning på minst 640x480 punkter med 24-bitars färg. Hela konstruktionen är uppbyggd kring Lattice^® MACH4A3-384/160. Designen av MACH kretsen är uppbyggd i Very High speed integrated hardware Description Language (VHDL) med hjälp av programmen ActiveHDL, Synplify Pro^®, ispDesignExpert samt LatticePRO. </p> / <p>This report is about the construction and fabrication of a video card for the Versa Module Euro card (VME) bus. The card will be used as a platform in laborations in courses including the VM42 microcontroller from PEP Modular Computer. The card is able to display a resolution of at least 640x480 pixels with 24bit color. The heart in the construction is the Lattice^® MACH4A3-384/160 Complex Programmable Logic Device (CPLD). All programming is done in Very High speed integrated hardware Description Language (VHDL) with the help of ActiveHDL, Synplify Pro^®, ispDesignExpert and LatticePRO software tools.</p>

Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen. / Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.

<p>Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen.</p> / <p>Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.</p>

This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) variable gain amplifier (VGA). The VGA design trade-off space is presented and methods for achieving an optimized design are discussed. We demonstrate in this thesis that SiGe HBT VGA has the capability to meet the demanding needs for the next generation wireless systems.

This thesis deals with designing and realisation of a bus analyzer. The analyzer is programmed into Spartan-3AN XC3S50AN programmable logic device. The design includes a SRAM parallel memory and a graphical LCD display. Data output is realized through USB, microSD memory card and VGA. The thesis also describes the use of a software microprocessor PicoBlaze for the control of the LCD display and user interface. The last part deals with a test application using an 8-bit microcontroller connected to an alphanumeric display and a discussion over the results.

This diploma thesis is about design of a 2D graphics controller for FPGA circuits. It consists of two parts. In the first phase, it analyses 2D acceleration and interface for communication with display devices of the operation system Linux. The second part contains design of graphics controller itself and its implementation. Part of the thesis is description of components that the controller consists of and evaluation of resultant implementation. For testing purposes on selected FPGA circuit, test modules adding support for used peripherals and test data generation are created.

This paper discusses the possibilities of realization of VGA grabber for FITkit. Text is focused on software and hardware implementation possibilities. The first part introduces the reader to the theory of the issue. Next, the paper proposes several options of VGA grabber implementation and brief evaluation of alternatives. The second part describes a chosen architecture of VGA grabber of the featured options and includes a brief summary of the findings of the processor LPC4370 from NXP and USB Video Class UVC, on which the resulting architecture is based. The conclusion includes a brief summary.

Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.