Denna rapport behandlar konstruktion och tillverkning av ett videokort till Versa Module Eurocard (VME) bussen. Kortet skall användas vid laborationer i kurser där mikrodatorkort VM42 från PEP Modular Computer används. Grafikkortet klarar en upplösning på minst 640x480 punkter med 24-bitars färg. Hela konstruktionen är uppbyggd kring Lattice® MACH4A3-384/160. Designen av MACH kretsen är uppbyggd i Very High speed integrated hardware Description Language (VHDL) med hjälp av programmen ActiveHDL, Synplify Pro®, ispDesignExpert samt LatticePRO. / This report is about the construction and fabrication of a video card for the Versa Module Euro card (VME) bus. The card will be used as a platform in laborations in courses including the VM42 microcontroller from PEP Modular Computer. The card is able to display a resolution of at least 640x480 pixels with 24bit color. The heart in the construction is the Lattice® MACH4A3-384/160 Complex Programmable Logic Device (CPLD). All programming is done in Very High speed integrated hardware Description Language (VHDL) with the help of ActiveHDL, Synplify Pro®, ispDesignExpert and LatticePRO software tools.

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

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The objective of this thesis is creating interface for the picture generator. The interface generates a VGA signal with possibility of 4bit color depth. The interface controls two chips of one port SRAM IS61 witch is supplied with Digilent Spartan-3 Starter Kit Board and comunicates trought FIFO blocks based on the shift register principle. Graphics interface generates lines and secondary forms, circles and secondary forms, fills area up and controles 2D transformations of picture.

Vga(A)LC and Msr(A) are clinically significant resistant proteins in staphylococci that confer resistance to translational inhibitors. They belong to ARE ABC-F protein subfamily, which is part of ABC transporters. Unlike typical ABC transporters, ABC-F proteins do not have transmembrane domains that are responsible for the transport of substances through the membrane. Therefore, they do not have characteristic transport function but regulatory or resistance function. Their mechanism of action on the ribosome has been described only recently, where these proteins displace the antibiotic from the ribosome. However, some aspects of their function are still unclear. For example, what is the function of the Vga(A) location on a membrane that has been detected in the membrane fraction but not in the ribosomal. In this work, using fluorescence microscopy, I observed subcellular localization of the Vga(A)LC-mEos2, Vga(A)LC-GFP and Msr(A)-eqFP650 resistant fusion proteins in live cells of S. aureus under different culture conditions . It has been shown that Vga(A)LC-GFP and Msr(A)-eqFP650 occur in a foci near the membrane. Depending on ATPase activity or the presence of an antibiotic, the localization of Msr(A)-eqFP650 in the cell changes from focal to diffuse, presumably on ribosomes, suggesting a...

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Τα τελευταία χρόνια η ανάγκη για αναλογικά ολοκληρωμένα κυκλώματα με χαμηλή τάση τροφοδοσίας και χαμηλή ισχύ γίνεται κάτι περισσότερο από επιτακτική. Ο βασικότερος λόγος για την ανάγκη αυτή είναι η ραγδαία ανάπτυξη από φορητές ηλεκτρονικές συσκευές για εφαρμογές πολυμέσων (laptops, netbooks, mobiles) έως ολοκληρωμένων συστημάτων βιοιατρικών εφαρμογών. Μάλιστα σε πολλές περιπτώσεις απαιτείται αυτές οι ηλεκτρονικές συσκευές να έχουν δυνατότητα διασύνδεσης σε ασύρματα δίκτυα (WLANs) και επομένως επιβάλλεται η ενσωμάτωση συστημάτων πομποδεκτών. Έτσι, οι απαιτήσεις για όσο το δυνατόν μικρότερη κατανάλωση και επομένως χαμηλότερη τροφοδοσία είναι επιβεβλημένες. Ένα από τα βασικότερα «δομικά» κυκλώματα σχεδίασης αναλογικών κυκλωμάτων είναι οι διαφορικοί ενισχυτές τάσης. Στην παρούσα διατριβή παρουσιάζονται πλήρεις λύσεις διαφορικών ενισχυτών χαμηλής τάσης τροφοδοσίας σε τυπική CMOS τεχνολογία των 0.35μm και 0.18μm. Οι προτεινόμενοι ενισχυτές σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα (Bulk-driven technique). Αρχικά σχεδιάστηκαν διαφορικοί ενισχυτές τάσεις με τοπολογία αρνητικής αντίστασης στην βαθμίδα εισόδου. Με τον τρόπο αυτό έγινε αύξηση της μικρής διαγωγιμότητας εισόδου που παρουσιάζει η τεχνική οδήγησης τρανζίστορ από το υπόστρωμα. Έτσι, προέκυψαν πρωτότυπες δομές ενισχυτών με χαμηλή τροφοδοσία μέχρι και 0.8V. Οι επιδόσεις των ενισχυτών χαρακτηρίστηκαν από κατάλληλες προσομοιώσεις αλλά και από πειραματικές μετρήσεις καθώς κατασκευάστηκε ολοκληρωμένο κύκλωμα ενισχυτή. Η σύγκλιση των αποτελεσμάτων των προσομοιώσεων με των πειραματικών απέδειξε πως τόσο τα προτεινόμενα κυκλώματα όσο και η ίδια η τεχνική σχεδίασης αποτελούν σημαντική λύση όπου απαιτούνται διαφορικοί ενισχυτές τάσης χαμηλής τροφοδοσίας. Στη συνέχεια σχεδιάστηκε βαθμίδα διαφορικού ακόλουθου τάσης με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και τροφοδοσία 1V. Η βαθμίδα αυτή χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου διαφορικού ενισχυτή τάσης με τροφοδοσία 1V. Ο ενισχυτής αυτός λειτουργεί για μεταβολή του κοινού σήματος εισόδου μεταξύ των άκρων της τροφοδοσίας. Ο ακόλουθος τάσης τροποποιήθηκε κατάλληλα ώστε να λειτουργεί με τροφοδοσία 0.5V και χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου σε διαφορικό ενισχυτή τάσης ίδιας τροφοδοσίας. Και οι δυο προτεινόμενες τοπολογίες ενισχυτών αποτελούν πλήρεις λύσεις για εφαρμογές ενισχυτών τάσης με χαμηλή και πολύ χαμηλή τροφοδοσία αντίστοιχα. Τέλος με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα σχεδιάστηκε ενισχυτής μεταβλητού κέρδους. Για το σκοπό αυτό αναπτύχθηκε τεχνική γραμμικής μεταβολής διαγωγιμότητας διαγωγών. Ο ενισχυτής μεταβλητού κέρδους που σχεδιάστηκε λειτουργεί με τροφοδοσία 0.8V ενώ το κέρδος έχει εύρος μεταβολής 17dB και μπορεί να ενσωματωθεί σε βρόχο αυτομάτου ελέγχου κέρδους χαμηλής τροφοδοσίας. Για το σκοπό αυτό σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και δυο κυκλώματα τετραγωνικής συνάρτησης με τροφοδοσία 0.8V και 0.5V αντίστοιχα. / In recent years the need for analog integrated circuits with low-voltage and low-power is more than urgent. The main reason for this need is the rapid growth of portable electronic devices for multimedia applications (laptops, netbooks, mobiles, etc.) and even more for biomedical devices applications. In many cases, these electronic devices provide connectivity to wireless networks (WLANs) and therefore they incorporate transceiver systems. Thus, requirements such as low-voltage and low-power are a necessity. One of the basic analog “building blocks” for circuit design is differential voltage amplifiers. This thesis presents complete solutions for low-voltage differential amplifiers in standard CMOS technology of 0.35μm and 0.18μm. The proposed amplifiers were designed with bulk-driven technique. In the first place are designed differential voltage amplifiers that include input stage with negative resistance circuitry. This way the proposed amplifiers improve the small input transconductance due to bulk-driven transistors. Thus, novel amplifier structures are obtained with a voltage supply equal even to 0.8V. The amplifiers performance is characterized both through simulation and experimental results. The convergence of simulation and experimental results demonstrate that the proposed amplifiers circuits designed with bulk-driven technique are significant solution in the design of low-voltage amplifiers. In the next step a differential bulk-driven voltage follower is designed with 1V voltage supply. The proposed follower is used as a differential input stage for a differential voltage amplifier with the same voltage supply. The proposed amplifier is capable to operate rail-to-rail for common mode input signals. Also, the proposed voltage follower is modified in order to operate in extreme voltage supply of 0.5V. The modified voltage follower is used, again, as a differential input stage for a differential voltage amplifier while the whole amplifier used a voltage supply equal to 0.5V. Both proposed amplifiers topologies that use bulk-driven differential voltage followers as input stages are complete solutions for low-voltage and ultra low-voltage amplifiers applications. Finally, a new technique for linear transconductance variation, applicable in any kind of transconductor, is introduced. The proposed technique is used to build a bulk-driven variable gain amplifier (VGA). The proposed VGA operate with 0.8V voltage supply while produce a gain range variation equal to 17dB. The amplifier could incorporate in an automatic gain control loop (AGC) for low-voltage applications. For this purpose, two bulk-driven voltage squarers circuits with voltage supply 0.8V and 0.5V was also proposed.

This thesis contains design of beamforming network designed for passive radar antennas. The first part contains theory of passive radars and beamforming networks. The next part implies design of beamforming network at the block digram level. Then are choosed circuits for amplitude and phase control, including the design of control communication. It follows by realization of IQ phase shifter and his automatic measurement. Based on this results is phase shifter adjusted and PCB of 2x2 beamforming network is designed. Last part includes design of control application (Matlab) and control program for STM32F407VG microcontroller.

LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.

This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted