We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level.

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional (3D) stacking technology has been studied [1, 2]. In our previous studies, wafer thinning effect using device wafers less than 10 μm was investigated [3, 4]. There was no change for the retention time before and after thinning even at 4 μm in thickness of DRAM wafer [5]. In this study, the behavior of Cu contamination on an ultra-thin Si stacked structure was investigated. Thinned Si wafers were intentionally contaminated with Cu on the backside and 250 °C of heating was carried out during the adhesive bonding and de-bonding processing. An approximately 200 nm thick damaged layer was formed at the backside of the Si wafer after thinning process and Cu particle precipitates ranged at 20 nm were observed by cross-sectional transmission electron microscopy (X-TEM). With secondary ion mass spectrometry (SIMS) and EDX analyses, Cu diffusion was not detected in the Si substrate, suggesting that the damaged layer prevents Cu diffusion from the backside.

The latest generation of semiconductor wafer fabs produce Integrated Circuits (ICs) on silicon wafers of 300mm diameter. In this dissertation, we address the following two types of (new) scheduling problems that are encountered in this generation of wafer fabs: multiple-lots-per-carrier scheduling problem (MLCSP) and integrated automated material handling and lot scheduling problem (IMHLSP). We consider several variations of the MLCSP depending upon the number of machines used, the prevailing processing technology of the machines, and the type of objective functions involved. For the IMHLSP, we study two instances, one with infinite number of vehicles and the other with finite number of vehicles. We begin by introducing a single-machine, multiple-lots-per-carrier with single-wafer-processing-technology scheduling problem for the objective of minimizing the total completion time (MLCSP1). The wafer carrier is a front-opening unified pod (FOUP) that can hold a limited number of wafers. The problem is easy to solve when all the lots are of the same size. For the case of different lot sizes, we first relax the carrier (FOUP) capacity and propose a dynamic programming-based algorithm, called RelaxFOUP-DP, which enables a quick determination of its optimal solution that serves as a lower bound for the problem with limited FOUP capacity. Then, a branch-and-bound algorithm, designated as MLCSP1-B&B, is developed that relies on the lower bound determined by the RelaxFOUP-DP algorithm. Numerical tests indicate that MLCSP1-B&B finds optimal solutions much faster than the direct solution of the MLCSP1 model by the AMPL CPLEX 10.1 Solver. In fact, for the medium and low density problems, the MLCSP1-B&B algorithm finds optimal solutions at the starting node (node zero) itself. Next, we consider a single-machine, multiple-lots-per-carrier with single-carrier-processing-technology scheduling problem for the objective of minimizing total completion time (MLCSP2). As for the case of MLCSP1, the optimal solution for the case in which all the lots are of the same size can be obtained easily. For the case of different lot sizes, we determine a lower bound and an upper bound for the problem and prove the worst-case ratios for them. Subsequently we analyze a two-machine flow shop, multiple-lots-per-carrier with single-wafer-processing-technology scheduling problem for the objective of minimizing the makespan (MLCSP3). We first consider a relaxed version of this problem, and transform the original problem to a two-machine flow shop lot streaming problem. Then, we propose algorithms to find the optimal capacitated sublot sizes for the case of lots with (1) the same ratio of processing times, and, (2) different ratios of processing times on the machines. Since the optimal solutions obtained from the lot streaming problem may not be feasible to the MLCSP3, we develop heuristic methods based on the heuristic procedures for the bin packing problem. We develop four heuristic procedures for lots with the same ratio of processing times, and another four procedures for lots with different ratios of processing times on the machines. Results of our numerical experimentation are presented that show that our heuristic procedures generate almost optimal solutions in a matter of a few seconds. Next, we address the integrated automated material handling and lot scheduling problem (IMHLSP) in the presence of infinite number of vehicles. We, first, propose a new strong hybrid model, which has the advantages of both segregate and direct models. In the segregate model, a job is always transferred to the stocker after its completion at a station, while in the direct model, it is transferred to the next machine in case that machine can accommodate the jobs; otherwise, the job will stay at current station. The decisions involved in the strong hybrid model are the sequence in which to process the lots and a selection between the segregate and direct models for each lot, whichever optimizes system performance. We show that, under certain conditions about the processing times of the lots, the problem can be approximated by the cases of either infinite buffer or zero-buffer at the machines. Hence, we consider all three cases of the IMHLSP in this chapter, namely, infinite buffer, zero-buffer, and limited buffer sizes. For the strong hybrid model with limited buffer size, we propose a branch-and-bound algorithm, which uses a modified Johnson's algorithm to determine a lower bound. Two upper bounds for this algorithm are also determined. Results of our numerical investigation indicate that our algorithm finds optimal solutions faster than the direct solution of the IMHLSP model by the AMPL CPLEX 10.1 Solver. Experimental results also indicate that for the same problem size, the times required to solve the IMHLSP model with interbay movements are larger than those for intrabay movements. Finally, we investigate the IMHLSP in the presence of limited number of vehicles. Due to the complex nature of the underlying problem, we analyze small-size versions of this problem and develop algorithms for their solution. For some of these problems, we can find optimal solutions in polynomial time. Also, based on our analysis on small-size systems, we have shown why some real-time dispatching (RTD) rules used in real fabs are expected to perform well while not the others. In addition, we also propose some new and promising RTD rules based on our study. / Ph. D.

Bei der Fertigung von Siliziumwafern durch Zerteilen eines Siliziumblockes kommt das Drahttrennläppverfahren zur Anwendung. Es wird eine Erregereinheit entwickelt, die den Siliziumblock während des Schneidprozesses zu Schwingungen anregt. Die Verwendung von Piezoaktoren ermöglicht mehrachsige Schwingungen mit variabler Frequenz und Amplitude. Wesentliche Bestandteile der Arbeit sind experimentelle Untersuchungen an den Aktoren und der gesamten Erregereinheit sowie die Modellierung des Gesamtsystems mit Hilfe linearer Einzelmodelle. Es zeigt sich, dass die Aktoren bei dynamischen Anwendungen linear beschrieben werden können, während das Gesamtmodell besonders in den Resonanzbereichen aufgrund montagebedingter Einflüsse Schwächen aufweist. Abschließend wird der Einfluss der Schwingungsanregung beim Drahtsägen untersucht. Aus den Versuchen geht hervor, dass im getesteten Frequenz- und Amplitudenbereich sowohl hohe Erregerfrequenzen als auch –amplituden geringere Schnittkräfte zur Folge haben.

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters. / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.

For mobile electronics such as Smartphones, Smartcards or wearable devices there is a trend towards an increasing functionality as well as miniaturisation. In this development Micro Electro- Mechanical Systems (MEMS) are an important key element for the realisation of functions such as motion detection. The specifications given by such devices together with the limited available space demand advanced packaging technologies. The 3D-Wafer Level Packaging (3D-WLP) enables one solution for a miniaturised MEMS package by using techniques such as Wafer Level Bonding (WLB) and Through Silicon Vias (TSV). This technology increases the effective area of the MEMS device by elimination dead space, which is typically required for other approaches based on wire bond assembly. Within this thesis, different TSV technology concepts with respect to a 3D-WLP for MEMS have been developed. Thereby, the focus was on a copper based technology as well as on two major TSV implementation methods. This comprises a Via Middle approach based on the separated TSV fabrication in the cap wafer as well as a Via Last approach with a TSV implementation in either the MEMS or cap wafer, respectively. For each option with its particular challenges, corresponding process modules have been developed. In the Via Middle approach, the wafer-related etch rate homogeneity determines the TSV reveal from the wafer backside Here, a reduction of the TSV depth down to 80 μm is favourable as long as the desired Cu-thermo-compression bonding (Cu-TCB) is performed before the thinning. For the TSV metallisation, a Cu electrochemical deposition method was developed, which allows the deposition of one redistribution layer as well as the bonding patterns for Cu-TCB at the same time. In the Via Last approach, the TSV isolation represents one challenge. Chemical Vapour Deposition processes have been investigated, for which a combination of PE-TEOS and SA-TEOS as well as a Parylene deposition yield the most promising results. Moreover, a method for the realisation of a suitable bonding surface for the Silicon Direct Bonding method has been developed, which does not require any wet pre treatment of the fabricated MEMS patterns. A functional MEMS acceleration sensor as well as Dummy devices serve as demonstrators for the overall integration technology as well as for the characterisation of electrical parameters.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207 / Im Bereich mobiler Elektronik, wie z.B. bei Smartphones, Smartcards oder in Kleidung integrierten Geräten ist ein Trend zu erkennen hinsichtlich steigender Funktionalität und Miniaturisierung. Bei dieser Entwicklung spielen Mikroelektromechanische Systeme (MEMS) eine entscheidende Rolle zur Realisierung neuer Funktionen, wie z.B. der Bewegungsdetektion. Die Anforderungen derartiger Bauteile zusammen mit dem begrenzten zur Verfügung stehenden Platz erfordern neuartige Technologien für die Aufbau- und Verbindungstechnick (engl. Packaging) der Bauteile. Das 3D-Wafer Level Packaging (3D-WLP) ermöglicht eine Lösung für eine miniaturisierte MEMS-Bauform unter Nutzung von Techniken wie dem Waferlevelbonden (WLB) und den Siliziumdurchkontaktierungen (TSV von engl. Through Silicon Via). Diese Technologie erhöht die effektive aktive Fläche des MEMS Bauteils durch die Reduzierung von Toträumen, welche für andere Ansätze wie der Drahtbond-Montage üblich sind. In der vorliegenden Arbeit wurden verschiedene Technologiekonzepte für den Aufbau von 3D-WLP für MEMS erarbeitet. Dabei lag der Fokus auf einer Kupfer-basierten Technologie sowie auf zwei prinzipiellen Varianten für die TSV-Implementierung. Dies umfasst den Via Middle Ansatz, welcher auf der TSV Herstellung auf einem separaten Kappenwafer beruht, sowie den Via Last Ansatz mit einer TSV Herstellung entweder im MEMS-Wafer oder im Kappenwafer. Für beide Varianten mit individuellen Herausforderungen wurden entsprechende Prozessmodule entwickelt. Beim Via Middle Ansatz ist die Wafer-bezogene Ätzratenhomogenität des Siliziumtiefenätzen entscheidend für das spätere Freilegen der TSVs von der Rückseite. Hier hat sich eine Reduzierung der TSV-Tiefe auf bis zu 80 μm vorteilhaft erwiesen insofern, das Kupfer-Thermokompressionsbonden (Cu-TKB) vor dem Abdünnen erfolgt. Zur Metallisierung der TSVs wurde ein Cu Galvanikprozess erarbeitet, welcher es ermöglicht gleichzeitig eine Umverdrahtungsebene sowie die Bondstrukturen für das Cu-TKB zu erzeugen. Beim Via Last Ansatz ist die TSV Isolation eine Herausforderung. Es wurden CVD (Chemische Dampfphasenabscheidung) Prozesse untersucht, wobei eine Kombination aus PE-TEOS und SA-TEOS sowie eine Parylene Beschichtung erfolgversprechende Ergebnisse liefern. Des Weiteren wurde eine Methode zur Erzeugung bondfähiger Oberflächen für das Siliziumdirektbonden erarbeitet, welche eine Nass-Vorbehandlung des MEMS umgeht. Ein realer MEMS-Beschleunigungssensor sowie Testaufbauten dienen zur Demonstration der Gesamtintegrationstechnologie sowie zur Charakterisierung elektrischer Parameter.:Bibliographische Beschreibung 3 Vorwort 13 List of symbols and abbreviations 15 1 Introduction 23 2 Fundamentals on MEMS and TSV based 3D integration 25 2.1 Micro Electro-Mechanical systems 25 2.1.1 Basic Definition 25 2.1.2 Silicon technologies for MEMS 26 2.1.3 MEMS packaging 29 2.2 3D integration based on TSVs 33 2.2.1 Overview 33 2.2.2 Basic processes for TSVs 34 2.2.3 Stacking and Bonding 47 2.2.4 Wafer thinning 48 2.3 TSV based MEMS packaging 50 2.3.1 MEMS-TSVs 50 2.3.2 3D-WLP for MEMS 52 3 Technology development for a 3D-WLP based MEMS 57 3.1 Target integration approach for 3D-WLP based MEMS 57 3.1.1 MEMS modules using 3D-WLP based MEMS 57 3.1.2 Integration concepts 58 3.2 Objective and requirements for the proposed 3D-WLP of MEMS 60 3.2.1 Boundary conditions 60 3.2.2 Technology concepts 63 3.3 Selected approaches for TSV implementation in MEMS 64 3.3.1 Via Last Technology 64 3.3.2 Via Middle technology 69 4 Development of process modules 75 4.1 Characterisation 75 4.2 TSV related etch processes 77 4.2.1 Equipment 77 4.2.2 Deep silicon etching 78 4.2.3 Etching of the buried dielectric layer 84 4.2.4 Patterning of TSV isolation liner – spacer etching 90 4.2.5 Summary 92 4.3 TSV isolation 93 4.3.1 Principle considerations 93 4.3.2 Experiment 95 4.3.3 Results 97 4.3.4 Summary 102 4.4 Metallisation of TSV and RDL 103 4.4.1 Plating base and experimental setup 103 4.4.2 Investigations related to the ECD process 106 4.4.3 Pattern plating 117 4.4.4 Summary 123 4.5 Wafer Level Bonding 124 4.5.1 Silicon direct bonding 124 4.5.2 Thermo-compression bonding by using ECD copper 128 4.5.3 Summary 134 4.6 Wafer thinning and TSV back side reveal 134 4.6.1 Thinning processes 134 4.6.2 TSV reveal processes 136 4.6.3 Summary 145 4.7 Under bump metallisation and solder bumps 146 5 Demonstrator design, fabrication and characterisation 149 5.1 Single wafer demonstrator for electrical test 149 5.1.1 Demonstrator design and test structure layout 149 5.1.2 Demonstrator fabrication 150 5.1.3 Electrical measurement 151 5.1.4 Summary 153 5.2 Via Last based TSV fabrication in the MEMS device wafer 153 5.2.1 Layout of the MEMS device with TSVs 153 5.2.2 Fabrication of TSVs and wafer thinning 154 5.2.3 Characterisation of the fabricated device 155 5.2.4 Summary 156 5.3 Via Last based cap-TSV for very thin MEMS devices 157 5.3.1 Design 157 5.3.2 Fabrication 158 5.3.3 Characterisation 161 5.3.4 Summary 162 5.4 Via Middle approach based on thinning after bonding 163 5.4.1 Design 163 5.4.2 Results and characterisation 164 5.4.3 Summary 166 6 Conclusion and outlook 167 Appendix A: Typical requirements on a MEMS package and its functions 171 Appendix B: Classification of packaging and system integration techniques 173 B.1 Packaging of electronic devices in general 173 B.2 Single Chip Packages 174 B.3 System integration 175 B.4 3D integration based on TSVs 180 Bibliography 183 List of figures 193 List of tables 199 Versicherung 201 Theses 203 Curriculum vitae 205 Own publications 207

Bei der Fertigung von Siliziumwafern durch Zerteilen eines Siliziumblockes kommt das Drahttrennläppverfahren zur Anwendung. Es wird eine Erregereinheit entwickelt, die den Siliziumblock während des Schneidprozesses zu Schwingungen anregt. Die Verwendung von Piezoaktoren ermöglicht mehrachsige Schwingungen mit variabler Frequenz und Amplitude. Wesentliche Bestandteile der Arbeit sind experimentelle Untersuchungen an den Aktoren und der gesamten Erregereinheit sowie die Modellierung des Gesamtsystems mit Hilfe linearer Einzelmodelle. Es zeigt sich, dass die Aktoren bei dynamischen Anwendungen linear beschrieben werden können, während das Gesamtmodell besonders in den Resonanzbereichen aufgrund montagebedingter Einflüsse Schwächen aufweist. Abschließend wird der Einfluss der Schwingungsanregung beim Drahtsägen untersucht. Aus den Versuchen geht hervor, dass im getesteten Frequenz- und Amplitudenbereich sowohl hohe Erregerfrequenzen als auch –amplituden geringere Schnittkräfte zur Folge haben.

Microelectronics integration continuously follows the trend of miniaturisation for which the technologies enabling fine pitch interconnection are in high demand. The recent advancement in the assembly of Hybrid Pixel Detectors, a high resolution detecting and imaging device, is an example of where novel materials and processes can be applied for ultra-fine pitch interconnections. For this application, indium is often used for the fine pitch bump bonding process due to its unique properties that make it especially suitable, in particular in a cryogenic environment where some types of detector have to serve. Indium bumps are typically fabricated through vacuum evaporation at the wafer level; however, this thesis investigates an alternative low cost manufacturing process at the wafer scale for the deposition of indium micro-bumps through electroplating. The work has placed its emphasis on the requirements of future technologies which will enable a low temperature (<150oC), high density interconnection (> 40,000 IOs/cm2) with a high throughput and high production yield. This research is a systematic investigation of the wafer-scale indium bumping process through electrodeposition using indium sulphamate solution. An intensive experimental study of micro-bump formation has been carried out to elaborate the effects of two of the main electroplating factors that can significantly influence the quality of bumps in the course of electrodeposition, namely the current distribution and mass transport. To adjust the current density distribution, various waveforms of current input, including direct current (DC), unipolar pulse current and bipolar pulse reverse current, were employed in the experiments. To assist mass transportation prior to or during electroplating, acoustic agitation including ultrasonic agitation at 30 kHz frequency as well as megasonic agitation at 1 MHz, were utilised. The electrochemical properties of the indium sulphamate solution were first investigated using non-patterned plain substrates prior to indium bumping trials. This provided understanding of the microstructural characteristics of indium deposits produced by electroplating and, through cathodic polarisation measurements, the highest current density suitable for electrodeposition was achieved as approximately 30 mA/cm2 when electroplating was carried out at room temperature and with no agitation applied. The typical surface morphology of DC electroplated indium contained a granular structure with a surface feature size as large as 10 µm. Pulse and pulse reverse electroplating significantly altered the surface morphology of the deposits and the surface became much smoother. By introducing acoustic agitation, the current density range suitable for electrodeposition could be significantly expanded due to the greater mass transfer, which led to a higher speed of deposition with high current efficiency. Wafer-scale indium bumping (15 µm to 25 µm diameter) at a minimum pitch size of 25 µm was successfully developed through electroplating trials with 3 inch test wafers and subsequently applied onto the standard 4 inch wafers. The results demonstrate the capability of electroplating to generate high quality indium bumps with ultrafine pitch at a high consistency and yield. To maximise the yield, pre-wetting of the ultrafine pitch photoresist patterns by both ultrasonic or megasonic agitation is essential leading to a bumping yield up to 99.9% on the wafer scale. The bump profiles and their uniformity at both the wafer and pattern scale were measured and the effects of electrodeposition regimes on the bump formation evaluated. The bump uniformity and microstructure at the feature scale were also investigated by cross-sectioning the electroplated bumps from different locations on the wafers. The growth mechanism of indium bumps were proposed on the basis of experimental observation. It was found that the use of a conductive current thief ring can homogenise the directional bump uniformity when the electrical contact is made asymmetrically, and improve the overall uniformity when the electrical contact is made symmetrically around the periphery of the wafer. Both unipolar pulse electroplating and bipolar pulse reverse electroplating improved the uniformity of the bump height at the wafer scale and pattern scale, and the feature scale uniformity could be significantly improved by pulse reverse electroplating. The best uniformity of 13.6% for a 4 inch wafer was achieved by using pulse reverse electroplating. The effect of ultrasonic agitation on the process was examined, but found to cause damage to the photoresist patterns if used for extended periods and therefore not suitable for use throughout indium bumping. Megasonic agitation enabled high speed bumping without sacrifice of current efficiency and with little damage to the photoresist patterns. However, megasonic agitation tended to degrade some aspects of wafer scale uniformity and should therefore be properly coupled with other electroplating parameters to assist the electroplating process.

La diminution des dimensions critiques dans l’industrie du semi-conducteur requiert l’utilisation de nouveaux matériaux fragiles qui dégradent la résistance mécanique des puces. On s’intéresse plus particulièrement aux étapes précédant la mise en boîtier, à savoir les tests paramétriques qui permettent de vérifier la fonctionnalité électrique de la puce, et les assemblages tels la connexion filaire qui ont pour but d’établir les connexions avec le boîtier. Durant ces opérations, des défaillances mécaniques sont observées dans les interconnexions situées sous le pad. Des techniques expérimentales (par ex : FIB/MEB) sont mises en œuvre une fois les tests ou les assemblages avec des fils d’or et de cuivre réalisés afin de mieux comprendre les raisons d’apparition de ces défaillances ainsi que leur localisation. Des plans d’expériences sont mis en place pour évaluer l’influence des divers paramètres de tests et d’assemblage et également celle des architectures de pad. En parallèle, une nouvelle méthode d’analyse basée sur la nanoindentation est utilisée pour comparer la robustesse mécanique de divers plots de connexion. D’autre part, plusieurs modèles éléments finis complexes, prenant en compte la gestion du contact entre la pointe de test et le pad ainsi que les effets inertiels associés, sont développés dans le but de reproduire les conditions de chargement sur les pads. Finalement, un ensemble d’outils adaptés à l’étude et l’optimisation des architectures de pad, dans une optique industrielle, est présenté de même que des règles de dessin permettant d’accompagner le développement technologique. / The diminution of the critical dimensions in the semiconductor industry and the introduction of new brittle dielectric materials raise questions on the mechanical resistance of the die and the pad architectures. Nowadays, pad structures are prone to crack. More precisely, the electrical wafer sort (EWS), which allows checking the electrical functionality of the die, and the assemblies such as the wire bonding to achieve the electrical connections with the packaging, are performed at the wafer level and introduce high levels of local mechanical stresses. Indeed, during these operations, failures in the oxide layers of the interconnections are observed. Experimental techniques (e.g. profilometry, FIB/SEM) are developed after EWS and bonding with gold and copper wires to gain insight on the root causes and localization of the failures. Some designs of experiments are set up to evaluate the influence of the test and process parameters and also of the various pad designs on the mechanical robustness of the structures. In addition, a novel analysis procedure, based on nanoindentation technique, is employed to compare various pads, which are complex multilayer systems. Moreover, several finite element models, using both explicit and implicit schemes are developed to mimic the EWS test. Indeed, these models have shown their ability to reproduce the loading conditions, the contact between the testing needle tip and the pad, and some inertial effect during the test. Finally, a comprehensive set of tools to evaluate and optimize the pad architectures is presented. Guidelines for pad layouts are also given, providing integration insights in the frame of the technology development.

L’utilisation des ultrasons pour l’imagerie présente plusieurs avantages : elle est extrêmement sure car ellen'utilise pas de radiations ionisantes et ne présente pas d'effets néfastes sur la santé. D’autre part, elle donne desrésultats d’excellente qualité avec un coût relativement faible. Historiquement, les matériaux piézoélectriques et leurscomposites ont été très tôt utilisés pour la génération d’ultrasons. Les transducteurs fabriqués à partir de ces matériauxdominent actuellement le marché des sondes ultrasonores. Cependant, pour certaines applications, ils ne peuvent pasêtre utilisés pour des raisons de dimensionnement et de limitations dues aux propriétés des matériaux. Une solutionpeut être apportée par l’utilisation des transducteurs ultrasonores capacitifs micro-usinés dits CMUTs. Ces dernierssuscitent un intérêt croissant dans le milieu de l’imagerie ultrasonore et sont considérés comme une alternativepotentielle et viable aux transducteurs piézoélectriques. Cette nouvelle technologie CMUTs est caractérisée par uneplus large bande passante, une sensibilité élevée, une facilité de fabrication et une réduction des coûts de production.Cette thèse est consacrée à la mise en place d’un certain nombre d’outils théoriques et expérimentaux permettant lamodélisation/conception, la fabrication et la caractérisation de transducteurs CMUTs à membrane circulaire pourl’émission des ultrasons. Nous commençons par développer des outils de simulation à base de calculs par élémentsfinis, permettant la compréhension et la modélisation du comportement électromécanique des CMUTs pour laconception et le dimensionnement des cellules élémentaires et des réseaux. Nous proposons par la suite un nouveauprocédé de fabrication de transducteurs CMUTs basé sur le collage anodique d’une couche de silicium monocristallind’épaisseur fixe d’une plaquette de SOI sur un substrat de verre. L’évolution du procédé de fabrication est détailléepour chaque étape technologique en soulignant à chaque fois les améliorations/modifications apportées pour unefiabilité et une répétitivité accrue associées à une connaissance des limites de faisabilité. Dans la dernière partie de cetravail, on s’intéresse à la mise en œuvre de plusieurs plateformes expérimentales permettant différentescaractérisations électromécaniques statiques et dynamiques des dispositifs CMUTs fabriqués / The use of ultrasound imaging has several advantages: it is extremely safe because it does not use ionizingradiation and has no adverse effects on health. It gives excellent quality results with a relatively low cost. Historically,piezoelectric materials and their composites have been early used for ultrasound generation. Transducers made fromthese materials dominate currently the ultrasonic probes market. However, for some applications, they can’t bebecause of design and limitation reasons due to material properties. A solution can be provided by the use ofcapacitive micromachined ultrasonic transducers CMUTs. A growing interest in the field of the ultrasound imaging isshown to this technology considered as a potential and viable alternative to piezoelectric transducers andcharacterized by a wide bandwidth, high sensitivity, ease of manufacture and reduce production costs. This thesis isdevoted to the establishment of a number of experimental and theoretical tools for the modeling/design, fabricationand characterization of circular membrane CMUTs transducers for ultrasound transmission. We begin by developingsimulation tools based on finite elements method in order to understand/model the CMUTs electromechanicalbehavior for the design and dimensioning of elementary cells and networks. Thereafter, we introduce a new CMUTtransducers fabrication process based on the anodic bonding a fixed thickness single crystal silicon layer of a SOIwafer on a glass substrate. The process evolution is detailed for each technological step highlighting everyimprovements/changes introduced for increased reliability and repeatability associated with an increased knowledgeof feasibility limits. In the last part of this work, we focus on the implementation of several experimental platformsallowing different static and dynamic electromechanical characterizations of the fabricated CMUTs devices.