We investigate some of the mechanical design factors of wafers and the effect on strength. Thin, solid, pre-stressed films are proposed as a means to improve the bulk mechanical properties of a wafer. Three-point bending was used to evaluate the laser scribe density and chemical processing effect on wafer strength. Drop and strike tests were employed to investigate the edge bevel profile effect on the mechanical properties of the wafer. To characterize the effect of thin films on strength, one-micron ceramic films were deposited on wafers using PECVD. Coated samples were prepared by cleaving and were tested using four-point bending. Film adhesion was characterized by notched four-point bending. RBS and FTIR were used to obtain film chemistry, and nanoindentation was used to investigate thin film mechanical properties. A stress measurement gauge characterized residual film stress. Mechanical properties of the wafers correlated to the residual stress in the film.

Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, sources of contamination from materials used in chemical handling was studied. The predominant anion contamination from fluoropolymers was found to be fluorides. Metallic contamination from fluoropolymers and polyethylene was also studied. The primary metal contamination comes from the actual fabrication of the polymer and not from the polymer resin.

No description available.

No description available.

Warped wafers and all the issues arise with them. are known issue in semiconductor industry. To solve those issues, the shape of the wafer needs to be known precisely. Current way of working when it comes to warped wafers is far from ideal within the company. A batch of wafers is acquired at customer’s site and it is assumed, that all the wafers in the batch are warped identically. A single specimen, representing the whole batch, is then taken to external company to be measured. As the method of measuring currently used contaminates and scratches the wafer, wafer must be scrapped afterwards. All the logistics and scrapped wafers add unnecessary costs to the company.  To optimize the warpage measuring procedure, a graduation internship project was initiated with a goal to develop a prototype of the tool, enabling inhouse warpage measuring.  The report contains all the methodology used to reach the final concept and results and includes methods such as: WBS, GANTT chart, Functional breakdown, Design requirement specification, Morphological matrix and PUGH’s matrix.  Final concept of warpage measuring tool consisted of implementing wafer sorting apparatus for wafer handling and enclosing the measuring tool to a custom housing, resembling a FOUP (Front Opening Unified Pod), allowing wafer sorting apparatus to load and unload test specimen for measuring. The measuring concept consists of rotary stage, where the wafer is loaded and rotated in addition to linear stage, that holds a confocal sensor above the wafer and moves it across the surface of the wafer, measuring the profile of the wafer, rotated every defined number of degrees between the measurements. Gravity induced deflection is eliminated by flipping the wafer using same wafer sorting apparatus and measuring the wafer inverted, thus allowing to estimate the true shape of the wafer.  The concept was developed in more detail, drawings for manufacturing the parts were created and the parts for building a functional prototype were ordered. Because of the COVID-19 pandemic, there were inevitable communication difficulties and delays in lead times, resulting in parts arriving on the last days of the internship, leaving no time for assembling and testing the actual prototype, therefore proof of concept is yet left to be tested by the employees of the company. / Vrängda kiselplattor och de problem som uppstår på grund av det är ett känt fenomen inom halvledarindustrin. För att kringgå dessa problem behövs god mätnoggranhet och det nuvarande sättet att hantera vrängda kiselplattor på inom företaget är långt från idealt. En batch kiselplattor hämtas hos kunden med antagandet att alla kiselplattor är identiskt vrängda. Ett enda exemplar som representerar hela batchen väljs sedan ut och skickas till ett externt mätföretag. Metoden som används för att mäta kiselplattan innehåller föroreningar och metoden repar även kiselplattan, som därmed inte kan användas efteråt. Utöver mätmetodens brister tillkommer även en utökad logistik och större materialspill som tillför kostnader för företaget.  Examensarbetets syfte är att förbättra mätmetoden som används för att utvärdera kiselplattornas vrängning och målet med projektet är att utveckla en prototyp som tillåter att mätmetoden görs internt inom företaget.  Rapporten innehåller metodiken som användes för att uppnå det slutgiltiga konceptet samt resultatet, och innehåller planeringsmoment samt projektets delmoment som: WBS, GANNT, funktionsnedbrytning, kravspecifikationer samt urvalsmatriser.  Det valda konceptet består av en sorteringsmaskin kombinerat med mätutrustningen och liknar en FOUP (Front Opening Unified Pod), vilket tillåter sorteringsmaskinen att tillföra och byta ut kiselplattorna som ska mätas. Mätutrustningen består av en roterande rörelse hos kiselplattan och en linjär rörelse hos en konfokal sensor placerad ovanför kiselplattan. Kombinationen av de båda rörelserna tillåter att hela kiselplattans yta mäts med ett givet vinkel- och radiellt steg. Genom att vända kiselplattan uppochner med sorteringsmaskinen och utföra samma mätning igen kan kiselplattans korrekta form estimeras genom att eliminera gravitationseffekten.  Konceptet utvecklades i detalj och tillverkningsunderlag och ritningar togs fram samt komponenter avsedda för tillverkning av en prototyp beställdes. På grund av COVID-19 pandemin uppstod dock kommunikationssvårigheter och förseningar i ledtider. Detta påverkade leveranserna och en del komponenter kom inte fram förrän i slutet av examensarbetet och det fanns därmed ingen tid över för montering eller tester som kan styrka konceptet, vilket får lämnas över till företagets anställda.

The objectives of this investigation are to develop a precise, non-destructive single crystal stress measurement technique, develop a model to explain the phenomenon known as 3power slump2, and investigate the role of device processing on wafer breakage. All three objectives were successfully met. The single crystal stress technique uses a least squares analysis of X-ray diffraction data to calculate the full stress tensor. In this way, precise non-destructive stress measurements can be made with known error bars. Rocking curve analysis, stress gradient corrections, and a data reliability technique were implemented to ensure that the stress data are correct. A theory was developed to explain 3power slump2, which is a rapid decrease in the amplifying properties of microwave amplifier circuits during operation. The model explains that for the particular geometry and bias configuration of the devices studied in this research, power slump is linearly related to shear stress at values of less than 90 MPa. The microscopic explanation of power slump is that radiation enhanced dislocation glide increases the kink concentration, thereby increasing the generation center concentration in the active region of the device. These generation centers increase the total gate current, leading to a decrease in the amplifying properties of the device. Passivation layer processing has been shown to both reduce the fracture strength and increase the residual stress in GaAs wafers, making them more susceptible to wafer breakage. Bare wafers are found to have higher fracture strength than passivated wafers. Bare wafers are also found to contain less residual stress than SiON passivated wafers, which, in turn, are found to have less stress than SiN passivated wafers. Topographic imaging suggests that SiN passivated wafers have larger flaws than SiON passivated wafers, and that the distribution of flaw size among SiN passivated wafers is wider than the distribution of flaws in SiON passivated wafers. These flaws are believed to lead to breakage of the device during processing, resulting in low fabrication yield. Both the power slump model and the wafer breakage data show that these phenomena are dependent on residual stress developed in the substrate during device fabrication. Reduction of process-induced residual stress should therefore simultaneously decrease wafer breakage rates and reduce power slump during device fabrication and operation. / Ph. D.

A low-cost, low-temperature packaging concept is proposed for localized sealing and control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro- Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices require application specific packaging to facilitate their integration, provide protection from the environment, and control interactions with other circuitry. In order to integrate these devices into standard integrated circuit (IC) process flows and minimize damage due to post-fabrication steps, packaging is performed at the wafer level. In this work Indium and Silver are used to seal a monolithic localized hermetic pack- age. The cavity protecting the device is formed using standard lithography-based processing techniques. Metal walls are built up from the substrate and encapsulated by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a predefined RF microsystem. The bond for the seal is then formed by rapid alloying of Indium and Silver using a temperature greater than that of the melting point of Indium. This ensures that the seal formed can subsequently function at temperatures higher than the melting temperature of pure Indium. This method offers a low-temperature bonding technique with thermal robustness suitable for wafer-level process integration. The ultimate goal is to create a seal in a vacuum environment. In this dissertation, design trade-offs made in wafer-level packaging are explained using thermo-mechanical stress and electrical performance simulations. Prototype passive microwave circuits are packaged using the developed packaging process and the performance of the fabricated circuits before and after packaging is analyzed. The effect of the package on coplanar waveguide structures are characterized by measuring scattering parameters and models are developed as a design tool for wafer-level package integration. The small scale of the localized package is expected to provide greater reliability over conventional full chip packages. / Ph. D.

Photolithography is the most complex of the operations involved in the fabrication of a wafer, and it requires the greatest precision. Photolithography is used to create multiple layers of circuit patterns on a chip. Traditionally, wafer fab operations, and in particular, those performed in the photolithography processing area, have always presented challenging scheduling and control problems. Some of the characteristics that make the photolithography processing area difficult to schedule are as follows: reentrant flow, unpredictable yield and rework time at critical operations, shared resources such as reticles, rapidly changing technologies, and lot dedication for steppers and scanners for critical layers. This processing area, where wafers are exposed using scanners or steppers, typically, comprises the bottleneck workstations. Also, the numbers of reticles available for a given layer of product type are limited. Consequently, it is important to develop appropriate schedules to ensure effective utilization of the tools involved. In this study, a manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in a photolithography area consisting of steppers and scanners (tools), with each product requiring a specific reticle type, determine the sequence in which to process the lots on the tools loaded with requisite reticles, so as to minimize the cycle time. The reticles required for processing a product are known apriori and can be transferred from one tool to another. Also, the lot dedication requirement has to be met. This requirement pertains to the fact that some of the layers of a lot should be processed on the same tool. (Scanner or Stepper). The processing of other layers may not require lot dedication. These are handled accordingly. Some lots may enter into the system with the requirement of processing them urgently. (called hot lots). These are handled in the formulation of the problem as such. Two solution methodologies are presented for the above stated problem. The first methodology uses a mathematical programming based approach. For the given routes and processing times of the product types, the entire problem is formulated as an Integer program. This integer program uses the start time of the jobs at various operations and the availability of reticles as variables, among others. The objective is to reduce the cycle time of the lots released into the system. The cycle time of a lot is defined as the time that a lot spends in the system. Results from the experimentation for integer program show that the computation time for solving small size problems is very high. A methodology is presented to solve this model efficiently. The second methodology consists of the development of a new dispatching rule for scheduling lots in the photolithography processing area. This along with the other dispatching rules discussed in the literature are implemented using the Autosched AP software to study the impact that lot dedication makes on the performance of a fab. The performance measures that are considered include throughput, cycle time, WIP and utilization of tool sets. The results are presented for 1-level, 2-level and 3-level lot dedication schemes. . It is shown that the 3- level lot dedication scheme performs the best under no preventive maintenance/breakdown case while, for the deterministic value of unscheduled breakdown times and preventive maintenance schedule used, 1-level lot dedication performed the best. Even though the 3-level lot dedication scheme is more flexible as compared to the 1–level lot dedication scheme, yet for the values of unscheduled breakdown times and preventive maintenance schedule used, the performance of the 3- level lot dedication scheme is worse than that of the 1- level lot dedication scheme. For another set of break down time values and preventive maintenance schedule, the outcome can be different. We also compare the performance of the proposed procedure with that of the dispatching rules available with the AutoSched AP software. The results indicate that the proposed procedure is consistent in generating better solutions under different operating conditions. / Master of Science

The semiconductor industry provides a host of very challenging problems in production planning and scheduling because of the unique features of the wafer fab. This research addresses the need to develop an approach, which can be used to generate optimal or near-optimal solutions to the scheduling problem of a wafer fab, by using Mathematical Programming for a general case of a wafer fab. The problem is approached in two steps. First, the number of lots of different products to be released into the system during each planning period is determined, such that the total tardiness of the product orders is minimized over the planning horizon. Second, the schedule of these lots is determined so that the cycle time of each lot released into the system is minimized. Thus, the performance measures based both on due dates and cycle time are considered. The lot release, tardiness problem is formulated as an integer linear program, and a 3-phase procedure, which utilizes a variation of the Wilkerson-Irwin algorithm, is developed. The performance of this 3-phase procedure is further improved by using insights from classical scheduling theory. The scheduling problem is formulated as a 0-1 integer linear program. An algorithm is developed for tightening the LP relaxation of this 0-1 integer linear programming model (of the scheduling problem) leading to a better performance of the branch and bound procedure used for its solution. Lagrangian relaxation is applied on a carefully chosen set of constraints in the scheduling problem, and a Lagrangian heuristic is developed for scheduling the jobs in each period of the planning horizon. Several useful insights are developed throughout to further improve the performance of the proposed algorithm. Experiments are conducted for both the tardiness and the scheduling problems. Five experiments are conducted for the tardiness problem. Each experiment has a different combination of number of products, machines, and work orders in a small sized wafer fab (2 to 6 products, 8 to 10 station families, 15 to 30 workstations, 9 to19 work orders, and 100 to 250 lots per work order). The solutions obtained by the 3-phase procedure are compared to the optimal solutions of the corresponding tardiness problems, and the tardiness per work order for the 3-phase procedure is 0% to 25% greater than the optimal solution. But the time required to obtain the optimal solution is 22 to 1074 times greater than the time required to obtain the solution through the 3-phase procedure. Thus, the 3-phase procedure can generate almost optimal solutions and requires much smaller computation time than that required by the optimal solution. Four experiments are conducted to test the performance of the scheduling problem. Each experiment has a different combination of number of products, machines, routes, bottleneck stations, processing times, and product mix entering the system each day in a small sized wafer fab (2 products, 8 station families, 18 workstations, and 8 to 10 lots released per day into the system). The solution quality of the schedule generated by the Lagrangian heuristic is compared to the solution provided by the standard dispatching rules available in practice. In each experiment, the cycle time of a product for each dispatching rule is divided by the best cycle time for that product over all the dispatching rules in that experiment. This ratio for the Lagrangian heuristic in each experiment and over all the experiments varies from 100% to 104%. For the standard dispatching rules, this ratio ranges from 100% to 120% in each experiment and also over all the experiments. The average of the ratio over all the experiments is the least for the Lagrangian heuristic. This indicates that for the experiments conducted, the Lagrangian heuristic consistently provides a solution that is, or is close to, the best solution and, hence, quite competitive when compared to the standard dispatching rules. / Master of Science

Sapphire fiber has been studied intensively for harsh environment sensing in the past two decades due to its supreme mechanical, physical and optical properties. It is by far the most reported and likely the best optical fiber based sensing technology for sensing applications in temperature beyond 1000°C. Several sensing schemes have been proposed and studied to date including sapphire fiber extrinsic and intrinsic Fabry-Perot interferometers, fiber Bragg gratings and long period gratings inscribed in sapphire fibers. Lacking the cladding, sapphire fiber is highly multi-moded which renders sapphire fiber based sensor fabrication much more difficult than those based on silica fibers. Among all the reported work on sapphire fiber sensing, the vast majority is for single point temperature measurement. In this work, different sensing schemes are proposed to enhance the capability of the sapphire fiber based sensing technology. For the single point sensing, a miniaturized sapphire fiber temperature sensor for embedded sensing applications was proposed and studied. The sensors are no more than 75 µm in diameter and are ideal for non-invasive embedded sensing applications. Unlike existing sapphire fiber sensors, the thin film sensors are batch-fabrication oriented and thus have a potential to permit mass production with low cost. In addition to single point sensors, multiplexed sapphire fiber sensing systems are investigated for the first time. Two multiplexed sensing solutions, named frequency-multiplexing and spatial-multiplexing, are proposed and studied to achieve multiplexed sensing based on sapphire fibers. / Ph. D.