Im Rahmen dieser Arbeit wurde der Prozess des chemisch-mechanischen Polierens (CMP) von Siliziumwafern erstmals mittels stochastischer Methoden modelliert und daraus resultierend weiter optimiert. Ziel war es, Erkenntnisse zu ausgewählten, noch nicht vollständig verstandenen Einflussfaktoren zu gewinnen. Der Schwerpunkt lag dabei auf dem Poliertuch. Anhand eines neu entwickelten Modells zur Beschreibung einer konditionierten Tuchoberfläche wurden Zusammenhänge zwischen Konditionier- bzw. Tuchstrukturparametern und resultierender Poliertuchoberfläche herausgearbeitet und somit Möglichkeiten zur exakten Beschreibung und der gezielten Beeinflussung letzterer ermittelt. Weiterhin konnte erstmalig ein lang gesuchter messbarer Parameter benannt werden, mit dem eine ideale Tuchoberfläche charakterisierbar wird. Die Ergebnisse wurden experimentell verifiziert. Abschließend wurde mit einem neuen Abtragsmodell der CMP-Prozess von Siliziumwafern beschrieben, anhand dessen Zusammenhänge zwischen der Tuchrauheit und der Unebenheit der Waferoberfläche mit einer Theorie begründbar wurden.

<p>Vertical-cavity surface-emitting lasers (VCSELs) areattractive as potential inexpensive high-performance emittersfor fibre-optical communication systems. Their surface-normalemission together with the small dimensions are beneficial forlow-cost fabrication since it allows on-wafer testing,simplified packaging and effective fibre-coupling. Forhigh-speed data transmission up to hundreds of metres, 850-nmVCSELs are today the technology of choice. For higher bandwidthand longer distance networks, emission at long-wavelength(1.3-1.55 µm) is required. Long-wavelength VCSELs are,however, not available since no materials system offershigh-index-contrast distributed Bragg reflectors (DBRs) as wellas high-gain active regions at such wavelengths.High-performance DBRs may be built up from AlGaAs/GaAsmultilayers, but long wavelength quantum wells (QWs) are onlywell established in the InP system. Therefore, the bestperforming devices have relied on wafer-fusion betweenInP-based QWs and AlGaAs-DBRs. More recently, however, the mainefforts have been shifted towards all-epitaxial GaAs-baseddevices, employing 1.3-µm GaInNAs QWs.</p><p>In this thesis, different processing technologies forlong-wavelength VCSELs are described. This includes a thoroughinvestigation of wafer-fusion between InP and GaAs regardingelectro-optical as well as metallurgical properties, and thedevelopment of a stable low-pressure process for the selectiveoxidation of AlAs. Optimised AlGaAs/GaAs DBRs were designed andfabricated. An important and striking observation from thatstudy is that n-type doping potentially is much moredetrimental to device performance than previously anticipated.These investigations were exploited in the realisation of twonew VCSEL designs. Near-room-temperature continuous-waveoperation of a single-fused 1.55-µm VCSEL was obtained.This demonstrated the potential of InGaAsP/InP DBRs inhigh-performance VCSELs, but also revealed a high sensitivityto self-heating. Further efforts were therefore directedtowards all-epitaxial GaAs-based structures. This resulted in ahigh-performance 1215-nm VCSEL with a highly strained InGaAssingle QW. This can be viewed as a basis for longer-wavelengthVCSELs, i.e., with an emission wavelength approaching 1300 nm,either by an extensive device detuning or with GaInNAs QWs.</p><p><b>Keywords</b>: VCSEL, vertical cavity laser, semiconductorlaser, long-wavelength, DBR, oxidation, wafer fusion, InGaAs,semiconductor processing</p>

Beim Aufbau von konfigurierbaren wafer-scale Systemen für pulsgekoppelte neuronale Netze werden hohe Anforderungen an die Kommunikation zwischen einzelnen Komponenten gestellt. Zur Unterstützung des Hardwareentwurfs, aber auch um die parallele Entwicklung der Software zu ermöglichen, können Simulationsmodelle verwendet werden. Der Aufbau der Architektur und die Implementierung als SystemC-Modell werden beschrieben. Aus der Simulation sind Rückschlüsse auf die Architektur möglich, es ergeben sich aber auch Anforderungen an die zu entwickelnde Softwareumgebung.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Farrokh Ayazi; Committee Member: James D. Meindl; Committee Member: Joy Laskar; Committee Member: Mark G. Allen; Committee Member: Paul A. Kohl. Part of the SMARTech Electronic Thesis and Dissertation Collection.

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

L'objectif de cette thèse est d'établir les liens entre élaboration, microstructure et comportement des getters non-évaporables (NEG) en couches minces, en vue de leur utilisation dans le cadre du packaging collectif des MEMS sous vide ou sous atmosphère contrôlée. Après une étude bibliographique sur l'herméticité des MEMS et l'effet getter, la modification du comportement de piégeage de gaz par les NEG couches minces, engendré par l'ajout de sous-couches métalliques, est mise en évidence. Afin d'expliquer cette influence, la microstructure des couches minces est étudiée, notamment sa dépendance aux paramètres d'élaboration et aux traitements thermiques. Ensuite, le comportement macroscopique de piégeage de l'azote est caractérisé, de même que les mécanismes microscopiques d'activation et de pompage. Ces derniers permettent finalement d'élaborer quelques recommandations pour l'intégration des NEG couches minces dans les MEMS.

Depuis l'invention du transistor dans les années 50, les performances des composants microélectroniques n'ont cessé de progresser, en passant notamment par l'augmentation de leur densité. Malheureusement, la miniaturisation des composants augmente les coûts de fabrication de façon prohibitive. Une solution, permettant d'accroître la densification et les fonctionnalités tout en limitant les coûts, passe par l'empilement des composants microélectroniques. Leurs connexions électriques s'effectuent alors à l'aide d'interconnexions verticales brasées au moyen d'un joint de brasure. Afin d'empêcher leurs ruptures lors des dilatations thermiques, les interconnexions sont protégées au moyen d'un polymère underfill. L'objectif de cette thèse est d'évaluer la faisabilité et la pertinence d'une nouvelle solution de remplissage par polymère, appelée wafer-level underfill (WLUF). L'écoulement de l'underfill durant l'étape d'assemblage des composants est modélisé afin de prédire les paramètres de scellement idéaux, permettant la formation des interconnexions électriques. Puis, l'intégration de nouveaux underfills, possédant des propriétés thermomécaniques différentes, pouvant affecter l'intégrité et le fonctionnement du dispositif, l'étude de la robustesse du procédé WLUF et, par conséquent, l'évaluation de sa possibilité d'industrialisation est effectuée.

In this thesis, we are making a new approach to fabricate silicon on insulator (SOI). By replacing the buried silicon dioxide and the silicon handling wafer with silicon carbide through hydrophilic wafer bonding, we have achieved silicon on crystalline silicon carbide for the first time and silicon on polycrystalline silicon carbide substrates at 150 mm wafer size. The conditions for the wafer bonding are studied and the surface and bond interface are characterized. Stress free and interfacial defect free hybrid wafer bonding has been achieved. The thermally unfavourable interfacial oxide that originates from the hydrophilic treatment has been removed through high temperature annealing, denoted as Ox-away. Based on the experimental observations, a model to explain the dynamics of this process has been proposed. Ox-away together with spheroidization are found to be the responsible theories for the behaviour. The activation energy for this process is estimated as 6.4 eV. Wafer bonding of Si and polycrystalline SiC has been realised by an intermediate layer of amorphous Si. This layer recrystallizes to some extent during heat treatment. Electronic and thermal testing structures have been fabricated on the 150 mm silicon on polycrystalline silicon carbide hybrid substrate and on the SOI reference substrate. It is shown that our hybrid substrates have similar or improved electrical performance and 2.5 times better thermal conductivity than their SOI counterpart. 2D simulations together with the experimental measurements have been carried out to extract the thermal conductivity of polycrystalline silicon carbide as κpSiC = 2.7 WK-1cm-1. The realised Si-on-SiC hybrid wafer has been shown to be thermally and electrically superior to conventional SOI and opens up for hybrid integration of silicon and wide band gap material as SiC and GaN.

Zugl.: Hagen, Fernuniv., Diss., 2007

Konstanz, Univ., Diplomarb., 2002.