Photovoltaic manufacturing is material intensive with the cost of crystalline silicon wafer, used as the substrate, representing 40% to 60% of the solar cell cost. Consequently, there is a growing trend to reduce the silicon wafer thickness leading to new technical challenges related to manufacturing. Specifically, wafer breakage during handling and/or transfer is a significant issue. Therefore improved methods for breakage-free handling are needed to address this problem. An important pre-requisite for realizing such methods is the need for fundamental understanding of the effect of handling device variables on the deformation, stresses, and fracture of crystalline silicon wafers. This knowledge is lacking for wafer handling devices including the Bernoulli gripper, which is an air flow nozzle based device. A computational fluid dynamics model of the air flow generated by a Bernoulli gripper has been developed. This model predicts the air flow, pressure distribution and lifting force generated by the gripper. For thin silicon wafers, the fluid model is combined with a finite element model to analyze the effects of wafer flexibility on the equilibrium pressure distribution, lifting force and handling stresses. The effect of wafer flexibility on the air pressure distribution is found to be increasingly significant at higher air flow rates. The model yields considerable insight into the relative effects of air flow induced vacuum and the direct impingement of air on the wafer on the air pressure distribution, lifting force, and handling stress. The latter effect is found to be especially significant when the wafer deformation is large. In addition to silicon wafers, the model can also be used to determine the lifting force and handling stress produced in other flexible materials. Finally, a systematic approach for the analysis of the total stress state (handling plus residual stresses) produced in crystalline silicon wafers and its impact on wafer breakage during handling is presented. Results confirm the capability of the approach to predict wafer breakage during handling given the crack size, location and fracture toughness. This methodology is general and can be applied to other thin wafer handling devices besides the Bernoulli gripper.

Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer bonding techniqueshave been reported in literature. In adhesive wafer bondingorganic and inorganic adhesives are used as intermediatebonding material. The main advantages of adhesive wafer bondingare the relatively low bonding temperatures, the lack of needfor an electric voltage or current, the compatibility withstandard CMOS wafers and the ability to join practically anykind of wafer materials. Adhesive wafer bonding requires nospecial wafer surface treatmentssuch as planarisation.Structures and particles at the wafer surfaces can be toleratedand compensated for some extent by the adhesive material.Adhesive wafer bonding is a comparably simple, robust andlowcost bonding process. In this thesis, adhesive wafer bondingtechniques with different polymer adhesives have beendeveloped. The relevant bonding parameters needed to achievehigh quality and high yield wafer bonds have been investigated.A selective adhesive wafer bonding process has also beendeveloped that allows localised bonding on lithographicallydefined wafer areas. Adhesive wafer bonding has been utilised in variousapplication areas. A novel CMOS compatible film, device andmembrane transfer bonding technique has been developed. Thistechnique allows the integration of standard CMOS circuits withthin film transducers that can consist of practically any typeof crystalline or noncrystalline high performance material(e.g. monocrystalline silicon, gallium arsenide,indium-phosphide, etc.). The transferred transducers or filmscan be thinner than 0.3 µm. The feature sizes of thetransferred transducers can be below 1.5 µm and theelectrical via contacts between the transducers and the newsubstrate wafer can be as small as 3x3 µm2. Teststructures for temperature coefficient of resistancemeasurements of semiconductor materials have been fabricatedusing device transfer bonding. Arrays of polycrystallinesilicon bolometers for use in uncooled infrared focal planearrays have been fabricated using membrane transfer bonding.The bolometers consist of free-hanging membrane structures thatare thermally isolated from the substrate wafer. Thepolycrystalline silicon bolometers are fabricated on asacrificial substrate wafer. Subsequently, they are transferredand integrated on a new substrate wafer using membrane transferbonding. With the same membrane transfer bonding technique,arrays of torsional monocrystalline silicon micromirrors havebeen fabricated. The mirrors have a size of 16x16 µm2 anda thickness of 0.34 µm. The advantages of micromirrorsmade of monocrystalline silicon are their flatness, uniformityand mechanical stability. Selective adhesive wafer bonding hasbeen used to fabricate very shallow cavities that can beutilised in packaging and component protection applications. Anew concept is proposed that allows hermetic sealing ofcavities fabricated using adhesive wafer bonding. Furthermore,microfluidic devices, channels and passive valves for use inmicro total analysis systems are presented. Adhesive wafer bonding is a generic CMOS compatible bondingtechnique that can be used for fabrication and integration ofvarious microsystems such as infrared focal plane arrays,spatial light modulators, microoptical systems, laser systems,MEMS, RF-MEMS and stacking of active electronic films forthree-dimensional high-density integration of electroniccircuits. Adhesive wafer bonding can also be used forfabrication of microcavities in packaging applications, forwafer-level stacking of integrated circuit chips (e.g. memorychips) and for fabrication of microfluidic systems.

Le packaging des MEMS-RF est un sujet de recherche qui a été étudié de manière intensive ces dernières années. En effet, la fiabilité des composants micromécaniques est directement dépendante de l’humidité et de la poussière avoisinant la structure. C’est pourquoi la recherche d'un package parfaitement hermétique à très faible coût, sans influence sur les performances RF reste d’actualité, même si un grand nombre de publications et de solutions ont été présentées auparavant. Ces travaux de recherche porte sur la conception, la réalisation et la caractérisation de commutateurs MEMS-RF ohmiques packagés par deux techniques différentes. La première partie de cette thèse a été consacrée d’étudier une encapsulation par film mince. Une couche métallique d’or électrolysée est utilisée pour former le capot, ensuite le nitrure de silicium est utilisé pour sceller le capot. Cette technique a présenté plusieurs avantages où nous obtenons une petite taille, l’augmentation du nombre de composants par substrat tout en réduisant le cout de fabrication. Malgré tous ces avantages, cette technique engendre aux composants des faibles effets parasites sur leurs performances RF. La deuxième technique qui a été étudié dans ce travail, est l’encapsulation par collage de tranche. Le principe de cette encapsulation est de sceller un substrat de capots micro-usinés en silicium avec un substrat contenant les composants MEMS-RF. Ensuite, une découpe de deux substrats est nécessaire pour obtenir les commutateurs MEMS-RF encapsulés. Le scellement utilisé durant cette thèse était le glass frit qui garantit une très bonne herméticité. Des mesures d’herméticité sont faites par le cnes montrent que les commutateurs mems-rf sont encapsulés hermétiquement en indiquant un taux de fuite de 8.8e-12 atm.cc/s. Les performances RF du commutateur MEMS-RF sont déjà présentées et qui montrent que cette technique d’encapsulation ne présente aucune influence sur ces performances. / RF MEMS packaging is an important research topic that is intensively studied for years. Indeed, Micro-mechanical devices that are protected from humidity, dust and working in a clean controlled atmosphere consequently improve their reliability. Meanwhile, the search for a perfectly hermetic package at very low cost with no influence on the RF performances is still a challenge even if a lot of publications and solutions have been presented so far. This research focuses on the design, realization and characterization of encapsulated RF MEMS switches using two different techniques. The first part of this thesis has been to study a Wafer Level Thin Film Packaging (WLTFP) using a metallic cap, then we have utilize the silicon nitride to seal this cap. This encapsulation technique presents several advantages where we have extremely small volume cavity, no double-wafer alignment required, and substantial increase in the number of devices per wafer reducing cost. Despite all these advantages, this technique generates to the components a low parasitic effects on their RF performances. Another type of packaging has been studied during this thesis is Wafer to Wafer Packaging. The principle of this encapsulation is to seal a micro-machined wafer of caps on the wafer containing RF MEMS switches to be protected. The both wafers are then cut together and we obtain directly the packaged switches. The RF MEMS packaging using this technique permits to obtain a hermetic package (leak rate of 8.8e-12 atm.cc/s measured by the French Space Agency-CNES) with no influence on the device characteristics. The RF characterization of the switch having a silicon cap bonded using a dielectric sealing paste have shown that the insertion loss in the ON state and the isolation in the OFF state is practically the same before and after capping.

In der vorliegenden Arbeit wurden experimentelle Untersuchungen zu Material begrenzenden Einflüssen beim Multidrahtsägen von Silicium unter Verwendung gerader und strukturierter Drähte durchgeführt. Ziel dieser Arbeit war es, den Einfluss von dünnen und strukturierten Drähten auf den Drahtsägeprozess von Silicium und die erzeugten Waferqualitäten zu untersuchen. Zusätzlich galt es, Grenzen und Potentiale für den Einsatz dieser Drähte im Sägeprozess aufzuzeigen und ein Modell zu entwickeln, das den Materialabtrag in Silicium für strukturierte Drähte beschreibt. Die in dieser Arbeit verfolgten Lösungsansätze beinhalten im ersten Teil der Arbeit die Durchführung von Sägeexperimenten mit einer Eindrahtsäge. Es wurden dünne Drähte mit Durchmesser ≤ 100 µm und zwei unterschiedliche Siliciumcarbid (SiC) Korngrößenverteilungen untersucht. Zusätzlich wurden die Normalkräfte in Vorschubrichtung variiert. Im zweiten Teil der Arbeit werden Sägeexperimente mit einer Multidrahtsäge vorgestellt. Es wurden zwei unterschiedlich strukturierte Drähte mit variierten Drahtgeschwindigkeiten und Vorschüben im Vergleich zu geradem Draht untersucht. Der industrielle Einsatz dünner Drähte im Sägeprozess zur Reduzierung des Sägeverschnitts ist derzeit auf Durchmesser von 100 µm begrenzt. Die getesteten Drähte mit geringerem Durchmesser sind nicht wirtschaftlich einsetzbar, da sie zu geringe Standzeiten aufweisen und zu einer Slurryverarmung beitragen können. Es konnte eine Slurryverarmung des Schnittspalts in Silicium beobachtet werden, die um mehrere Zentimeter in den Schnittspalt ragt und dadurch den Drahtsägeprozess negativ beeinflusst, indem Sägeriefen entstehen. Die Verschleißuntersuchungen von Sägedrähten zeigen, dass eine lineare Abnahme der Drahtdurchmesserreduzierung in Abhängigkeit der akkumulierten Eingriffslänge in Silicium auftritt. Der Prozess der Durchmesserreduzierung wird maßgeblich durch die aufgebrachte Normalkraft, welche durch die Zugfestigkeit und Härte des Drahts beeinflusst wird, die Drahtgeschwindigkeit und die verwendete Korngrößenverteilung bestimmt. Es konnte durch Sägeversuche mit Drähten unterschiedlicher Hersteller gezeigt werden, dass das beobachtete Verschleißverhalten nicht einem Drahthersteller zuordenbar ist, sondern eine globalere Gültigkeit besitzt. Der industrielle Einsatz strukturierter Drähte wirkt sich positiv auf den Sägeprozess aus. Es konnten signifikant höhere Vorschübe bei ähnlichen Kräften im Vergleich zu geraden Drähten erreicht werden. Für einen Vorschub von 0,6 mm/min sind die Kraftwerte für strukturierten Draht A im Vergleich zu geradem Draht um 40% reduziert, für Draht B um 16%. Durch die Drahtstruktur wird ein größeres Slurryvolumen durch den Schnittspalt befördert, was zu einem homogeneren Materialabtrag entlang des Schnittspalts führt. Die erhöhten Vorschübe konnten sowohl für mono- wie auch für multikristallines Siliciummaterial erreicht werden. Zusätzlich wurden homogenere Waferdicken durch den Einsatz strukturierter Drähte beim Sägeprozess erzeugt. Auf Basis der Ergebnisse für strukturierte Drähte wurde ein theoretisches Modell für den Materialabtrag entwickelt, welches die in dieser Arbeit durchgeführten Experimente gut beschreibt. / In the present work experimental analyses were carried out to investigate the material limiting influences in the multi wire sawing process of silicon while using thin and structured wires. The purpose of the work was to investigate influences on the wire sawing process and the resulting wafer qualities caused by thin and structured wires. Additionally, the purpose was to define the limits and potentials of thin and structured wires in industrial wire sawing processes and to develop a model which describes the material removal in silicon for structured wires. Experiments with two different SiC particle size distributions in combination with wire diameters of ≤ 100 µm and varying normal forces in feed direction were carried out in the first part of this work with a single wire saw. Experiments with two differently structured wires and variation of the wire speed and feed rate are shown in the second part using a multi wire saw. The actual limit for industrial sawing applications to reduce kerf loss is reached for 100 µm thin wire diameters. The tested lower wire diameters are uneconomical due to shorter durability and to aggravate slurry depletion effects. Such a depletion effect of several centimeters length which is detrimental for the wire sawing process was observed at the end of a sawing channel. The results of the experiments showed that the steel wire diameter is reduced linearly with the accumulated sawn length of silicon. The material removal process of the steel wire is significantly influenced by the normal force in feed direction and the hardness of the wire. The experiments with wires of different suppliers showed no difference in the material removal process. Therefore the abrasive wear of wires has a more global validation. The results of the experiments using differently structured wires showed that significantly lower forces in feed direction occur for a given feed rate in comparison to straight wires. The forces are reduced up to 40% for structured wire A and up to 16% for wire B for a feed rate of 0,6 mm/min. A higher slurry volume is transported due to the structure of the wire which enables a more homogeneous material removal process along the cutting channel. Higher feed rates were reached for mono- and multi crystalline silicon material. Additionally, more homogeneous wafer thicknesses were cut using structured wires.

Ce travail de thèse vise la définition et la mise au point de technologies pour l'empilement depuces microélectroniques dans un polymère et connectées électriquement par des viastraversants. Il explore deux voies : l’une de caractère industriel, utilisant une résine époxychargée en billes de silice E2517, l'autre, plus exploratoire, est basée sur l'utilisation de laSU8.Nous avons travaillé sur la mise au point des différentes étapes permettant d'empiler 4niveaux de puces amincies à 80 microns (enrobées) et empilées sur des épaisseurs de l'ordredu millimètre. Le problème du perçage des vias a été abordé et étudié à travers la mise aupoint de procédés d'usinage au laser des résines de type industriel. La métallisation encouches minces de ces trous de facteur de forme élevée (20) a été menée de sorte à atteindredes valeurs de résistance d'accès les plus faibles possibles.Un comparatif des deux voies utilisant la SU8 et la résine E2517 a été effectué et ses résultatscommentés en termes de faisabilité techniques et ses projections dans le domaine industriel.Des tests de fiabilité thermomécaniques ont été menés de concert avec une modélisation paréléments fini afin de valider les résultats des expérimentations réalisées dans le cadre de cetteétude / The subject of this thesis is the definition and development of TPV (Through Polymer Via)technology to stacking chips. The principal objective is to increase the potentialities of thevertical staking (complex IC; multiple I/O...) of Si chips without loss of performance or yield.The technique used consists to surround the IC chips by using particular resin and to fill (withmetallic films) the vertical holes drilled in this material. It explores two ways: one of anindustrial character, using an epoxy resin filled with silica beads E2517, other, moreexploratory, is based on the use of SU8.We worked on the development of different stages to stack four levels of chips thinned to 80microns (coated) and stacked on the thickness of one millimeter. The problem of drilling viashas been discussed and studied through the development of laser drilling processes ofindustrial resins. The thin-film metallization of the holes of high aspect ratio (20) wasconducted in order to reach values of access resistance as low as possible.A comparison of the two channels using SU8 resin and E2517 was carried out and the resultsdiscussed in terms of technical feasibility and its projections in the industrial field.Thermomechanical reliability tests were conducted in conjuction with finite element modelingto validate the results of experiments conducted in this study.

With increasing frequency up to the THz frequency range and the desire to optimize performance of modern applications, precise knowledge of the dielectric material parameters of a substrate being used in a planar application is crucial: High performance of the desired device or circuit can often be achieved only by properly designing it, using specific values for the material properties. Especially the integration of planar devices for very broadband applications at high frequencies often demands specific dielectric properties such as a low permittivity, dispersion and loss, assuring a predictable performance over a broad frequency range. Therefore, material characterization at these frequencies is of interest to the developing THz community, although not a lot of methods suitable in terms of frequency range and measurement setup exist yet. In this work, a comprehensive method for dielectric material parameter determination from S-Parameter measurements of unloaded and loaded planar transmission lines up to THz frequencies is developed. A measurement setup and methodology based on wafer prober measurements is established, which allows for characterization of planar substrates and bulk material samples alike. In comparison with most existing methods, no specialized measurement cell or cumbersome micro-machining of material samples is necessary. The required theory is developed, including a discussion of effective parameter extraction methods from measurement, identification of and correction for undesired transmission line effects such as higher order modes, internal inductance and surface roughness, as well as mapping and modelling procedures based on physical permittivity models and electromagnetic simulations. Due to the general approach and modular structure of the developed method, new models to cover additional aspects or enhance its performance even further are easily implementable. Measurement results from 100 MHz to 500 GHz for planar substrates and from 100 MHz to 220 GHz for bulk material samples emphasize the general applicability of the developed method. It is inherently broadband, while the upper frequency limit is only subject to the fabrication capabilities of modern planar technology (i.e. minimum planar dimensions of transmission lines and height of substrate) and thus is easily extendable to higher frequencies. Furthermore, the developed method is not bound to a specific measurement setup and applicable with other measurement setups as well, as is exemplary presented for a free-space setup using antennas, enabling measurement of large, flat material samples not fitting on the wafer prober. Several substrate and bulk material samples covering a wide range of permittivities and material classes are characterized and compared with reference values from literature and own comparison measurements. The uncertainties for both planar substrate as well as bulk material sample measurements are estimated with a single-digit percentage. For all measurements, the order of magnitude of the dielectric loss tangent can be determined, while the lower resolution boundary for bulk material sample measurements is estimated to 0.01. Concerning measurements in the wafer prober environment, fixture-related issues are a main cause of measurement uncertainty. This topic is discussed as well as the design of on-wafer probe pads and custom calibration standards required for broadband operation at THz frequencies. / Mit zunehmender Erschließung des THz-Frequenzbereichs und der zugehörigen Optimierung moderner Anwendungen ist eine genaue Kenntnis der dielektrischen Materialparameter verwendeter planarer Substrate unabdingbar: Eine hohe Performance angestrebter Bauteile oder Schaltungen kann nur durch einen präzisen Entwurf sichergestellt werden, wofür spezifische Werte für die Materialeigenschaften bekannt sein müssen. Insbesondere die Integration planarer Bauelemente für sehr breitbandige Anwendungen bei hohen Frequenzen bedingt spezifische dielektrische Materialeigenschaften, wie bspw. geringe Permittivität, Dispersion und Verluste, sodass eine vorhersagbare Performance über einen breiten Frequenzbereich sichergestellt werden kann. Materialcharakterisierung bei diesen Frequenzen ist folglich von Interesse für die sich entwickelnde THz-Forschungslandschaft, wenngleich derzeit kaum Verfahren existieren, die geeignet in Bezug auf den Frequenzbereich oder Messaufbau sind. Im Rahmen dieser Arbeit wird ein umfassendes Verfahren zur Bestimmung der dielektrischen Materialparameter aus S-Parameter-Messungen unbelasteter und belasteter planarer Leitungen bis in den THz-Bereich entwickelt. Ein Messaufbau mitsamt Messmethodik basierend auf Wafer Prober-Messungen wird entworfen, welcher die Charakterisierung von planaren Substraten und losen Materialproben ermöglicht. Im Vergleich zu existierenden Verfahren ist weder eine spezielle Messzelle noch eine umständliche Mikrobearbeitung der Materialproben notwendig. Die Entwicklung der hierfür notwendigen Theorie beinhaltet eine Diskussion von Methoden zur Extraktion effektiver Parameter aus Messungen, die Identifikation und Korrektur unerwünschter Leitungseffekte wie bspw. höherer Moden, interner Induktivität und Oberflächenrauhigkeit sowie Zuordnungs- und Modellierungsverfahren basierend auf physikalischen Permittivitätsmodellen und elektromagnetischen Simulationen. Durch den allgemeinen, modularen Ansatz des entwickelten Verfahrens lassen sich neue Modelle zur Berücksichtigung zusätzlicher Effekte oder weiteren Verbesserung der Performance einfach einarbeiten. Messergebnisse von 100 MHz bis 500 GHz für planare Substrate und von 100 MHz bis 220 GHz für lose Materialproben unterstreichen die allgemeine Anwendbarkeit des entwickelten Verfahrens. Es ist inhärent breitbandig, wobei eine obere Frequenzgrenze nur durch die Fertigungstoleranzen moderner planarer Technologien gegeben ist (minimale Leitungsdimensionen und Substrathöhe), sodass es einfach zu höheren Frequenzen hin erweiterbar ist. Weiterhin ist das entwickelte Verfahren nicht an einen bestimmten Messaufbau gebunden und auch mit weiteren Aufbauten anwendbar, wie beispielhaft an einem Freiraum-Aufbau mit Antennen präsentiert wird. Eine Vielzahl planarer Substrate und loser Materialproben, die ein weites Spektrum an Permittivitäten und Materialklassen abdecken, werden charakterisiert und mit Referenzdaten aus der Literatur sowie eigenen Messungen verglichen. Die Messunsicherheiten der Permittivitätsmessungen werden im einstelligen Prozentbereich abgeschätzt und der dielektrische Verlustwinkel kann in seiner Größenordnung bestimmt werden. Aufbaubezogene Einflüsse als eine Hauptursache für Messunsicherheiten am Wafer Prober werden adressiert, ebenso wie der Entwurf von On-Wafer Probe Pads und selbsterstellter Kalibrierstandards, die notwendig sind für den Einsatz bei THz-Frequenzen.

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping.

We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level.

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional (3D) stacking technology has been studied [1, 2]. In our previous studies, wafer thinning effect using device wafers less than 10 μm was investigated [3, 4]. There was no change for the retention time before and after thinning even at 4 μm in thickness of DRAM wafer [5]. In this study, the behavior of Cu contamination on an ultra-thin Si stacked structure was investigated. Thinned Si wafers were intentionally contaminated with Cu on the backside and 250 °C of heating was carried out during the adhesive bonding and de-bonding processing. An approximately 200 nm thick damaged layer was formed at the backside of the Si wafer after thinning process and Cu particle precipitates ranged at 20 nm were observed by cross-sectional transmission electron microscopy (X-TEM). With secondary ion mass spectrometry (SIMS) and EDX analyses, Cu diffusion was not detected in the Si substrate, suggesting that the damaged layer prevents Cu diffusion from the backside.

In this dissertation, three types of microfabricated solid-state sensors had been designed and developed on silicon wafers, aiming to detect hydrogen gas at elevated temperatures. Based on the material properties and sensing mechanisms, they were operated at 140°C, 500°C, and 300°C. The MOS-capacitor device working at 140°C utilized nickel instead of the widely-used expensive palladium, and the performance remained excellent. For very-high temperature sensing (500°C), the conductivity of the thermally oxidized TiO2 thin film based on the anodic aluminum oxide (AAO) substrate changed 25 times in response to 5 ppm H2 and the response transient times were just a few seconds. For medium-high temperatures (~300°C), very high sensitivity (over 100 times’ increment of current for H2 concentration at 10 ppm) was obtained through the reversible reduction of the Schottky barrier height between the Pt electrodes and the SnO2 nano-clusters. Fabrication approaches of these devices included standard silicon wafer processing, thin film deposition, and photolithography. Materials characterization methods, such as scanning electron microscopy (SEM), atomic force microscopy (AFM), surface profilometry, ellipsometry, and X-ray diffractometry (XRD), were involved in order to investigate the fabricated nano-sized structures. Selectivities of the sensors to gases other than H2 (CO and CH4) were also studied. The first chapter reviews and evaluates the detection methodologies and sensing materials in the current research area of H2 sensors and the devices presented this Ph.D. research were designed with regard to the evaluations.