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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
41

Effects of the Machining Conditions on Polishing Mechanism of Silicon Wafer for the Continuous Composite Electroplated Polisher

Yang, Sheng-Shiu 28 July 2004 (has links)
In the study, the effects of the machining conditions, ex, machining positions, loads and rotating speed ratio on machining mechanism of wafer are investigated by using the continuous composite electroplated polisher and find the best machining conditions of the polisher. Experimental results show that when the wafer and polisher are full contact, the operating of machinery is most smooth and the flatness is better. When the load is increased, the reducing rate of average roughness¡]Ra¡^and maximum roughness¡]Rmax¡^, removal rate, and the speed of mirror degree are increased. The machining mechanism and the stability of machinery is depended on the value of rotating speed ratio. In the different rotating speed ratio, the flatness of wafer is difference. For example, the rotating speed ratio is 1, the flatness is 1.5 £gm/38 mm. The rotating speed ratio is 2, the flatness is 2.3 £gm/38 mm. Finally, choose the rotating speed ratio, which the values of rotating speed are close and complex on the range of rotating speed which machinery can be operating most stable in machining process. Because of the machining mechanism are similar and the grinding locus are finer. Hence, the flatness of wafer becomes better. When the rotating speed ratio is 1.1, the flatness is 1.46£gm/38 mm. The rotating speed ratio is 1.11, the flatness is 1.45£gm/38 mm. The effect of the rotating speed ratio of the wafer and polisher on the grinding locus type of grinding surface is theoretically analyzed. Results show that when the rotating speed ratio is irregular, the distribution of grinding locus becomes finer. The analyzable results of locus and provable results of experiment are the same.
42

Ananysis of Thermal-Flow in Chemical Vapor Deposition

Wang, Chii-Ming 23 July 2001 (has links)
Abstract The development and advancement of microelectronics industry is very drastically. So, the key to create new technology of process and it's costs can be cut by simulating the performance of these equipments. The reactor of chemical vapor deposition (CVD) is important to semiconductor production process.. This research use numerical method to study the process parameters of low-pressure chemical vapor deposition (LPCVD) of Tungsten (W).In this simulation, the CVD reactor modeling are constructed and discreditzed by using the implicit finite volume method. The grids are arranged in a staggered manner for the discretization of the governing equations. Then, the SIMPLE-type algorithm will be used to solve all of the discretized algebra equations. In this research, the reactor is an single wafer and cold-wall system. The nozzle position is adjustable from 100 to 250mm.The nozzle-to-wafer distance is adjustable by changing the height from 30 to 120mm.The temperature and pressure in the reactor system can be setup with susceptor temperature 300~600 and pressure 0.5~8Torr. The results show that the flow in the reactor may depend on the flow rate and nozzle position. An effective means to avoid unstable is to reduce the susceptor temperature and system pressure due to the effects of buoyancy force and recirculation.
43

Wafer Planarization by Cylindrical Polishing Process

Weng, Chun-Cheng 28 June 2002 (has links)
This thesis is aimed to apply cylindrical polishing system to a large flat workpiece (ex:wafer) to obtain high degree of planarization, low surface roughness and no crack layer. First, a mathematical model is presented which describes the axially symmetric form error compensation by cylindrical polishing process. The dwelling time-distribution of tool and the machining depth distribution are solved using the methods of simultaneous equations and least square error with non-negativity constraints. Then, using the simulation analysis and experimental method to examine the machining rate distribution effects on machining precision and the dwelling time-distribution of the tool when the workpiece is machining by cylindrical tool. The examined effects will include machining length effect, boundary effect and inclined effect. Under the range of the machining precision required, the approach to smooth the dwelling time-distribution of tool that will benefit layer-by-layer removing strategy. After these analyses, an adequacy dwelling time-distribution of the tool can be designed according to the workpiece form error. In addition, the relative between the machining probability due to the an-isotropic polishing property and surface roughness will be discussed. The contents of this thesis include three parts. First, a mathematical model is presented which describes the axially symmetric form error compensation by cylindrical polishing process. And, the polishing angles and polishing probability of the an-isotropic polishing property will be identified according to the mathematical model. Second, the design of dwelling time-distribution of tool and the analysis of the geometric effects will be discussed by computer simulation. Third, the experimental results will show the suitable of the machining strategy and compare the machining effects with the simulated results. And, the planarization of the workpiece that has axially symmetric form error will be done.
44

Lead Free Bump Assembly Material and Structure Study for 40 nm Wafer Technology

Wang, Tai-sheng 02 February 2010 (has links)
Solder bump is used to connect organic substrate with chip to form Flip Chip package. Comparing to wire bond package, the path is reduced so the electrical performance is much better. Due to the environmental concern, eutectic bump is replaced by lead-free bump gradually. Meanwhile, since wafer technology is improved from 55 nm to 40 nm, the material for dielectric layers is also changed so the material for the package need to revised to meet the characteristic of wafer. Now the laser grooving is adopted before blade sawing to accommodate the brittleness of new 40nm wafer. Also, one extra polyimide is added in the wafer fabrication to reinforce the robustness of the circuit. The stress inside the lead-free bump can be reduced by optimizing the temperature of the reflow process and the speed of cooling. Different UBM structure is also reviewed to find out its affect on the strength of bump and low-K circuit so the failure mode of bump can be predicted. The selection of underfill need to be well considered so, the warpage of package can be reduced, the maximum protection of bump and low-K circuit can be achieved, and the process is easier to control. (The four underfills are reviewed) The reliability test is utilized to decide the best bump composition, the structure of UBM, the selection of underfills and the process parameter. By adding the laser grooving in the wafer sawing process, the chance of crack on die low-K layer is reduced during the reliability test. As for the UBM structure, the POU is better than RPI to reduce the crack of die low-K layer. The result is verified on the package with no underfill by Temperature cycle. Last, the matching of SnCu0.7 bump with SAC305 C4 pad has the best result. During the research, the variance of CTE for the core of substrate contributes less warpage of package, comparing to the difference of Tg for underfills. The adhesion of underfills varies and the underfill UA9 has the best result. The flip chip package with underfill UA9 can passes TCB1000. The optimization of UBM structure for lead-free bump is researched and discussed. Composition of the lead-free bump, process parameter, and cost, those factors are also studied.
45

Automatic semiconductor wafer map defect signature detection using a neural network classifier

Radhamohan, Ranjan Subbaraya 21 February 2011 (has links)
The application of popular image processing and classification algorithms, including agglomerative clustering and neural networks, is explored for the purpose of grouping semiconductor wafer defect map patterns. Challenges such as overlapping pattern separation, wafer rotation, and false data removal are examined and solutions proposed. After grouping, wafer processing history is used to automatically determine the most likely source of the issue. Results are provided that indicate these methods hold promise for wafer analysis applications. / text
46

Compliant Wafer Level Package (CWLP)

Patel, Chirag Suryakant 05 1900 (has links)
No description available.
47

High-Speed Probe Card Analysis Using Real-time Machine Vision and Image Restoration Technique

Shin, Bonghun January 2013 (has links)
There has been an increase in demand for the wafer-level test techniques that evaluates the functionality and performance of the wafer chips before packaging them, since the trend of integrated circuits are getting more sophisticated and smaller in size. Throughout the wafer-level test, the semiconductor manufacturers are able to avoid the unnecessary packing cost and to provide early feedback on the overall status of the chip fabrication process. A probe card is a module of wafer-level tester, and can detect the defects of the chip by evaluating the electric characteristics of the integrated circuits(IC's). A probe card analyzer is popularly utilized to detect such a potential probe card failure which leads to increase in the unnecessary manufacture expense in the packing process. In this paper, a new probe card analysis strategy has been proposed. The main idea in conducting probe card analysis is to operate the vision-based inspection on-the- y while the camera is continuously moving. In doing so, the position measurement from the encoder is rstly synchronized with the image data that is captured by a controlled trigger signal under the real-time setting. Because capturing images from a moving camera creates blurring in the image, a simple deblurring technique has been employed to restore the original still images from blurred ones. The main ideas are demonstrated using an experimental test bed and a commercial probe card. The experimental test bed has been designed that comprises a micro machine vision system and a real-time controller, the con guration of the low cost experimental test bed is proposed. Compared to the existing stop-and-go approach, the proposed technique can substantially enhance the inspection speed without additional cost for major hardware change.
48

Grafting of polymers onto SiO 2 surfaces through surface-attached monomers

Mädge, Daniel. January 2007 (has links)
Freiburg i. Br., Univ., Diss., 2007.
49

Dynamic parameter identification techniques and test structures for microsystems characterization on wafer level

Shaporin, Alexey January 2009 (has links)
Zugl.: Chemnitz, Techn. Univ., Diss., 2009
50

Positronenspektroskopie an plastischen Zonen in Al-Legierungen und GaAs-Wafern

Zamponi, Christiane. Unknown Date (has links) (PDF)
Universiẗat, Diss., 2002--Bonn.

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